From: Luke Kenneth Casson Leighton Date: Fri, 29 Jan 2021 18:42:08 +0000 (+0000) Subject: adjust how register copy/setup is done in PowerDecoder2 X-Git-Tag: convert-csv-opcode-to-binary~296 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b880743fc00132212224690939106ada62202d09;p=soc.git adjust how register copy/setup is done in PowerDecoder2 --- diff --git a/libreriscv b/libreriscv index c63a58b3..30348c76 160000 --- a/libreriscv +++ b/libreriscv @@ -1 +1 @@ -Subproject commit c63a58b326a2b17d617b098261f217409c65402c +Subproject commit 30348c765a545765ebe16121738730d17174f955 diff --git a/src/soc/decoder/power_decoder2.py b/src/soc/decoder/power_decoder2.py index 0f4c16a2..579b56e0 100644 --- a/src/soc/decoder/power_decoder2.py +++ b/src/soc/decoder/power_decoder2.py @@ -866,11 +866,14 @@ class PowerDecode2(PowerDecodeSubset): comb += dec_o2.lk.eq(do.lk) # registers a, b, c and out and out2 (LD/ST EA) - comb += e.read_reg1.eq(dec_a.reg_out) - comb += e.read_reg2.eq(dec_b.reg_out) - comb += e.read_reg3.eq(dec_c.reg_out) - comb += e.write_reg.eq(dec_o.reg_out) - comb += e.write_ea.eq(dec_o2.reg_out) + for to_reg, fromreg in ( + (e.read_reg1, dec_a.reg_out), + (e.read_reg2, dec_b.reg_out), + (e.read_reg3, dec_c.reg_out), + (e.write_reg, dec_o.reg_out), + (e.write_ea, dec_o2.reg_out)): + comb += to_reg.data.eq(fromreg.data) + comb += to_reg.ok.eq(fromreg.ok) # SPRs out comb += e.read_spr1.eq(dec_a.spr_out)