From: Daniel Benusovich <flyingmonkeys1996@gmail.com>
Date: Mon, 22 Apr 2019 06:45:43 +0000 (-0700)
Subject: Add lfsr with 11 bits
X-Git-Tag: div_pipeline~2177^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8929ab6f8ce605b60e6ee4cbd45f3c84ae1d427;p=soc.git

Add lfsr with 11 bits
---

diff --git a/TLB/src/LFSR.py b/TLB/src/LFSR.py
new file mode 100644
index 00000000..4e0fe7d5
--- /dev/null
+++ b/TLB/src/LFSR.py
@@ -0,0 +1,30 @@
+from nmigen import Module, Signal
+from nmigen.cli import main
+
+size = 11
+
+class LFSR:
+    def __init__(self):
+
+        # Output
+        self.enable = Signal(1)
+        self.o = Signal(size)
+
+    def elaborate(self, platform=None):
+        m = Module()
+
+        for i in range(size):
+            with m.If(self.enable):
+                if i == 0:
+                    zero = self.o[0]
+                    one = self.o[1]
+                    m.d.sync += self.o[0].eq(zero ^ one)
+                if i == 3:
+                    zero = self.o[0]
+                    three = self.o[4]
+                    m.d.sync += self.o[3].eq(zero ^ three)
+                else:
+                    prev = self.o[(i + 1) % size]
+                    m.d.sync += self.o[i].eq(prev)
+        return m
+
diff --git a/TLB/test/test_lfsr.py b/TLB/test/test_lfsr.py
new file mode 100644
index 00000000..0b476adc
--- /dev/null
+++ b/TLB/test/test_lfsr.py
@@ -0,0 +1,30 @@
+import sys
+sys.path.append("../src")
+sys.path.append("../../TestUtil")
+
+from nmigen.compat.sim import run_simulation
+
+from LFSR import LFSR
+
+from test_helper import assert_eq, assert_ne, assert_op
+
+def testbench(dut):
+    yield dut.enable.eq(1)
+    yield dut.o.eq(9)
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+    yield
+
+if __name__ == "__main__":
+    dut = LFSR()
+    run_simulation(dut, testbench(dut), vcd_name="Waveforms/test_lfsr.vcd")
+    print("LFSR Unit Test Success")
\ No newline at end of file