From: lkcl <lkcl@web>
Date: Tue, 7 Jun 2022 18:05:40 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~1915
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8b5ea7d913011ef7a60b6a926c861c48a1b43af;p=libreriscv.git

---

diff --git a/openpower/sv/compliancy_levels.mdwn b/openpower/sv/compliancy_levels.mdwn
index 0b3c06ef0..854926552 100644
--- a/openpower/sv/compliancy_levels.mdwn
+++ b/openpower/sv/compliancy_levels.mdwn
@@ -50,5 +50,10 @@ JIT Translation or Illegal Instruction traps.  SVSTATE joins MSR and PC
 as direct peers and must be switched on any context-switch (Trap or
 Exception)
 
+* PC is saved/restored to/from SRR0
+* MSR is saved/restored to/from SRR1
+* SVSTATE **must** also be saved/restored to/from SVSRR1
 
-* MSR is saved/restored to SRR1
+Any implementation that implements Hypervisor Mode must also
+correspondingly follow the Power ISA Spec for HSRR0 and HSRR1,
+and must save/restore SVSTATE to/from HSVSRR1.