From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 16 Jul 2019 06:22:00 +0000 (+0100)
Subject: add full coverage fcvt up 32 to 64 test
X-Git-Tag: ls180-24jan2020~831
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8c17d40cbbbc02d9efec02eaf712a3521e81086;p=ieee754fpu.git

add full coverage fcvt up 32 to 64 test
---

diff --git a/src/ieee754/fcvt/test/test_fcvt_up_pipe_32_64.py b/src/ieee754/fcvt/test/test_fcvt_up_pipe_32_64.py
new file mode 100644
index 00000000..9c24dc22
--- /dev/null
+++ b/src/ieee754/fcvt/test/test_fcvt_up_pipe_32_64.py
@@ -0,0 +1,21 @@
+""" test of FPCVTMuxInOut
+"""
+
+from ieee754.fcvt.pipeline import (FPCVTUpMuxInOut,)
+from ieee754.fpcommon.test.case_gen import run_pipe_fp
+from ieee754.fpcommon.test import unit_test_single
+from ieee754.fcvt.test.up_fcvt_data_32_64 import regressions
+
+from sfpy import Float64, Float32
+
+def fcvt_64(x):
+    return Float64(x)
+
+def test_pipe_fp32_64():
+    dut = FPCVTUpMuxInOut(32, 64, 4)
+    run_pipe_fp(dut, 32, "upfcvt", unit_test_single, Float32,
+                regressions, fcvt_64, 10, True)
+
+if __name__ == '__main__':
+    test_pipe_fp32_64()
+
diff --git a/src/ieee754/fcvt/test/up_fcvt_data_32_64.py b/src/ieee754/fcvt/test/up_fcvt_data_32_64.py
new file mode 100644
index 00000000..aa0b2e65
--- /dev/null
+++ b/src/ieee754/fcvt/test/up_fcvt_data_32_64.py
@@ -0,0 +1,4 @@
+# yes, 0x0 was a regression :)
+def regressions():
+    yield 0x0,
+    yield 0x0,