From: lkcl <lkcl@web>
Date: Sat, 26 Dec 2020 22:08:00 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~824
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8c79f80c11ad3339b66e7d802d5224373babfc1;p=libreriscv.git

---

diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn
index 12f80db61..8641fb08f 100644
--- a/openpower/sv/overview.mdwn
+++ b/openpower/sv/overview.mdwn
@@ -50,7 +50,7 @@ The fundamentals are:
 * The Program Counter (PC) gains a "Sub Counter" context (Sub-PC)
 * Vectorisation pauses the PC and runs a Sub-PC loop from 0 to VL-1
   (where VL is Vector Length)
-* The Program Order of "Sub-PC" instructions must be preserved,
+* The [[Program Order]] of "Sub-PC" instructions must be preserved,
   just as is expected of instructions ordered by the PC.
 * Some registers may be "tagged" as Vectors
 * During the loop, "Vector"-tagged register are incremented by