From: Gabriel Somlo <gsomlo@gmail.com>
Date: Sat, 1 Aug 2020 21:06:02 +0000 (-0400)
Subject: soc/interconnect/axi: add Wishbone2AXI converter
X-Git-Tag: 24jan2021_ls180~36^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8c9da81ea504023a642f7d2593788fd8f59b49d;p=litex.git

soc/interconnect/axi: add Wishbone2AXI converter
---

diff --git a/litex/soc/interconnect/axi.py b/litex/soc/interconnect/axi.py
index 958061a9..ec25bbae 100644
--- a/litex/soc/interconnect/axi.py
+++ b/litex/soc/interconnect/axi.py
@@ -649,6 +649,15 @@ class Wishbone2AXILite(Module):
             NextState("IDLE")
         )
 
+# Wishbone to AXI ----------------------------------------------------------------------------------
+
+class Wishbone2AXI(Module):
+    def __init__(self, wishbone, axi, base_address=0x00000000):
+        axi_lite          = AXILiteInterface(axi.data_width, axi.address_width)
+        wishbone2axi_lite = Wishbone2AXILite(wishbone, axi_lite, base_address)
+        axi_lite2axi      = AXILite2AXI(axi_lite, axi)
+        self.submodules += wishbone2axi_lite, axi_lite2axi
+
 # AXILite to CSR -----------------------------------------------------------------------------------
 
 def axi_lite_to_simple(axi_lite, port_adr, port_dat_r, port_dat_w=None, port_we=None):