From: Florent Kermarrec Date: Thu, 27 Jun 2019 21:28:12 +0000 (+0200) Subject: targets: use new prefered way to add wishbone slave X-Git-Tag: 24jan2021_ls180~1138 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8d45af5c39d693619180f2ab675fd56e52678eb;p=litex.git targets: use new prefered way to add wishbone slave --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index 7b36a493..4e3a0a07 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import arty from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -85,7 +84,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index ac426075..d025340e 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import genesys2 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -78,7 +77,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index 0a6205c3..4bb90216 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -12,7 +12,6 @@ from migen import * from litex.boards.platforms import kc705 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -80,7 +79,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index e6106aab..04670b82 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import kcu105 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -117,7 +116,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 2f98e0bc..13d69754 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import netv2 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -82,7 +81,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index d1c451ff..00f07116 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import nexys4ddr from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -84,7 +83,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index 39b23526..ad78f538 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -10,7 +10,6 @@ from migen import * from litex.boards.platforms import nexys_video from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -82,7 +81,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index f0af059e..f8bcd948 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -43,7 +43,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index b0a15ff3..9094992f 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -12,7 +12,6 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.boards.platforms import versa_ecp5 from litex.soc.cores.clock import * -from litex.soc.integration.soc_core import mem_decoder from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * @@ -116,7 +115,7 @@ class EthernetSoC(BaseSoC): self.add_csr("ethphy") self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac") diff --git a/litex/tools/litex_sim.py b/litex/tools/litex_sim.py index b255d917..b0238ce1 100755 --- a/litex/tools/litex_sim.py +++ b/litex/tools/litex_sim.py @@ -17,7 +17,6 @@ from litex.soc.integration.soc_core import * from litex.soc.integration.soc_sdram import * from litex.soc.integration.builder import * from litex.soc.cores import uart -from litex.soc.integration.soc_core import mem_decoder from litedram.common import PhySettings from litedram.modules import MT48LC16M16 @@ -153,7 +152,7 @@ class SimSoC(SoCSDRAM): if with_etherbone: ethmac = ClockDomainsRenamer({"eth_tx": "ethphy_eth_tx", "eth_rx": "ethphy_eth_rx"})(ethmac) self.submodules.ethmac = ethmac - self.add_wb_slave(mem_decoder(self.mem_map["ethmac"]), self.ethmac.bus) + self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"] | self.shadow_base, 0x2000) self.add_csr("ethmac") self.add_interrupt("ethmac")