From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Thu, 12 Feb 2015 00:19:36 +0000 (+0100)
Subject: move generic modules to generic/__init__.py
X-Git-Tag: 24jan2021_ls180~2604^2~27
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8f2fc2290f0666487c00e25e78944176eaa9d46;p=litex.git

move generic modules to generic/__init__.py
---

diff --git a/liteeth/common.py b/liteeth/common.py
index 25562dc1..cea70727 100644
--- a/liteeth/common.py
+++ b/liteeth/common.py
@@ -278,153 +278,3 @@ def eth_etherbone_mmap_description(dw):
 		("be", dw//8)
 	]
 	return EndpointDescription(payload_layout, param_layout, packetized=True)
-
-# Generic classes
-class Port:
-	def connect(self, port):
-		r = [
-			Record.connect(self.source, port.sink),
-			Record.connect(port.source, self.sink)
-		]
-		return r
-
-# Generic modules
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class FlipFlop(Module):
-	def __init__(self, *args, **kwargs):
-		self.d = Signal(*args, **kwargs)
-		self.q = Signal(*args, **kwargs)
-		self.sync += self.q.eq(self.d)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Counter(Module):
-	def __init__(self, signal=None, **kwargs):
-		if signal is None:
-			self.value = Signal(**kwargs)
-		else:
-			self.value = signal
-		self.width = flen(self.value)
-		self.sync += self.value.eq(self.value+1)
-
-@DecorateModule(InsertReset)
-@DecorateModule(InsertCE)
-class Timeout(Module):
-	def __init__(self, length):
-		self.reached = Signal()
-		###
-		value = Signal(max=length)
-		self.sync += If(~self.reached, value.eq(value+1))
-		self.comb += self.reached.eq(value == (length-1))
-
-class BufferizeEndpoints(ModuleDecorator):
-	def __init__(self, submodule, *args):
-		ModuleDecorator.__init__(self, submodule)
-
-		endpoints = get_endpoints(submodule)
-		sinks = {}
-		sources = {}
-		for name, endpoint in endpoints.items():
-			if name in args or len(args) == 0:
-				if isinstance(endpoint, Sink):
-					sinks.update({name : endpoint})
-				elif isinstance(endpoint, Source):
-					sources.update({name : endpoint})
-
-		# add buffer on sinks
-		for name, sink in sinks.items():
-			buf = Buffer(sink.description)
-			self.submodules += buf
-			setattr(self, name, buf.d)
-			self.comb += Record.connect(buf.q, sink)
-
-		# add buffer on sources
-		for name, source in sources.items():
-			buf = Buffer(source.description)
-			self.submodules += buf
-			self.comb += Record.connect(source, buf.d)
-			setattr(self, name, buf.q)
-
-class EndpointPacketStatus(Module):
-	def __init__(self, endpoint):
-		self.start = Signal()
-		self.done = Signal()
-		self.ongoing = Signal()
-
-		ongoing = Signal()
-		self.comb += [
-			self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
-			self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
-		]
-		self.sync += \
-			If(self.start,
-				ongoing.eq(1)
-			).Elif(self.done,
-				ongoing.eq(0)
-			)
-		self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
-
-class PacketBuffer(Module):
-	def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
-		self.sink = sink = Sink(description)
-		self.source = source = Source(description)
-
-		###
-		sink_status = EndpointPacketStatus(self.sink)
-		source_status = EndpointPacketStatus(self.source)
-		self.submodules += sink_status, source_status
-
-		# store incoming packets
-		# cmds
-		def cmd_description():
-			layout = [("error", 1)]
-			return EndpointDescription(layout)
-		cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
-		self.submodules += cmd_fifo
-		self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
-		if hasattr(sink, "error"):
-			self.comb += cmd_fifo.sink.error.eq(sink.error)
-
-		# data
-		data_fifo = SyncFIFO(description, data_depth, buffered=True)
-		self.submodules += data_fifo
-		self.comb += [
-			Record.connect(self.sink, data_fifo.sink),
-			data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
-			self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
-		]
-
-		# output packets
-		self.fsm = fsm = FSM(reset_state="IDLE")
-		self.submodules += fsm
-		fsm.act("IDLE",
-			If(cmd_fifo.source.stb,
-				NextState("SEEK_SOP")
-			)
-		)
-		fsm.act("SEEK_SOP",
-			If(~data_fifo.source.sop,
-				data_fifo.source.ack.eq(1)
-			).Else(
-				NextState("OUTPUT")
-			)
-		)
-		if hasattr(source, "error"):
-			source_error = self.source.error
-		else:
-			source_error = Signal()
-
-		fsm.act("OUTPUT",
-			Record.connect(data_fifo.source, self.source),
-			source_error.eq(cmd_fifo.source.error),
-			If(source_status.done,
-				cmd_fifo.source.ack.eq(1),
-				NextState("IDLE")
-			)
-		)
-
-		# compute almost full
-		if almost_full is not None:
-			self.almost_full = Signal()
-			self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
\ No newline at end of file
diff --git a/liteeth/core/__init__.py b/liteeth/core/__init__.py
index 6a143c9c..4d9b7147 100644
--- a/liteeth/core/__init__.py
+++ b/liteeth/core/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac import LiteEthMAC
 from liteeth.core.arp import LiteEthARP
 from liteeth.core.ip import LiteEthIP
diff --git a/liteeth/core/arp/__init__.py b/liteeth/core/arp/__init__.py
index fbc31da0..58b7aa89 100644
--- a/liteeth/core/arp/__init__.py
+++ b/liteeth/core/arp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 
diff --git a/liteeth/core/etherbone/__init__.py b/liteeth/core/etherbone/__init__.py
index 8186193d..78f3d738 100644
--- a/liteeth/core/etherbone/__init__.py
+++ b/liteeth/core/etherbone/__init__.py
@@ -1,8 +1,7 @@
 from liteeth.common import *
-
+from liteeth.generic import *
 from liteeth.generic.arbiter import Arbiter
 from liteeth.generic.dispatcher import Dispatcher
-
 from liteeth.core.etherbone.packet import *
 from liteeth.core.etherbone.probe import *
 from liteeth.core.etherbone.record import *
diff --git a/liteeth/core/etherbone/packet.py b/liteeth/core/etherbone/packet.py
index 1426db37..22f72c5a 100644
--- a/liteeth/core/etherbone/packet.py
+++ b/liteeth/core/etherbone/packet.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 
diff --git a/liteeth/core/etherbone/probe.py b/liteeth/core/etherbone/probe.py
index a447532c..04eb9f6a 100644
--- a/liteeth/core/etherbone/probe.py
+++ b/liteeth/core/etherbone/probe.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthEtherboneProbe(Module):
 	def __init__(self):
diff --git a/liteeth/core/etherbone/record.py b/liteeth/core/etherbone/record.py
index 2ce52517..008be002 100644
--- a/liteeth/core/etherbone/record.py
+++ b/liteeth/core/etherbone/record.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 
diff --git a/liteeth/core/etherbone/wishbone.py b/liteeth/core/etherbone/wishbone.py
index d49e4341..2f5b1762 100644
--- a/liteeth/core/etherbone/wishbone.py
+++ b/liteeth/core/etherbone/wishbone.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from migen.bus import wishbone
 
 class LiteEthEtherboneWishboneMaster(Module):
diff --git a/liteeth/core/icmp/__init__.py b/liteeth/core/icmp/__init__.py
index 35a69cc9..79c51925 100644
--- a/liteeth/core/icmp/__init__.py
+++ b/liteeth/core/icmp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 
diff --git a/liteeth/core/ip/__init__.py b/liteeth/core/ip/__init__.py
index 00204aa4..17f854cb 100644
--- a/liteeth/core/ip/__init__.py
+++ b/liteeth/core/ip/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.core.ip.common import *
 
 class LiteEthIPTX(Module):
diff --git a/liteeth/core/ip/common.py b/liteeth/core/ip/common.py
index 17102767..8f27cdd5 100644
--- a/liteeth/core/ip/common.py
+++ b/liteeth/core/ip/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar
diff --git a/liteeth/core/udp/__init__.py b/liteeth/core/udp/__init__.py
index 16ad1b8b..1bac7b72 100644
--- a/liteeth/core/udp/__init__.py
+++ b/liteeth/core/udp/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.core.udp.common import *
 
 class LiteEthUDPTX(Module):
diff --git a/liteeth/core/udp/common.py b/liteeth/core/udp/common.py
index 187b829e..c5a2d472 100644
--- a/liteeth/core/udp/common.py
+++ b/liteeth/core/udp/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar
diff --git a/liteeth/generic/__init__.py b/liteeth/generic/__init__.py
index e69de29b..643e9872 100644
--- a/liteeth/generic/__init__.py
+++ b/liteeth/generic/__init__.py
@@ -0,0 +1,151 @@
+from liteeth.common import *
+
+# Generic classes
+class Port:
+	def connect(self, port):
+		r = [
+			Record.connect(self.source, port.sink),
+			Record.connect(port.source, self.sink)
+		]
+		return r
+
+# Generic modules
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class FlipFlop(Module):
+	def __init__(self, *args, **kwargs):
+		self.d = Signal(*args, **kwargs)
+		self.q = Signal(*args, **kwargs)
+		self.sync += self.q.eq(self.d)
+
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class Counter(Module):
+	def __init__(self, signal=None, **kwargs):
+		if signal is None:
+			self.value = Signal(**kwargs)
+		else:
+			self.value = signal
+		self.width = flen(self.value)
+		self.sync += self.value.eq(self.value+1)
+
+@DecorateModule(InsertReset)
+@DecorateModule(InsertCE)
+class Timeout(Module):
+	def __init__(self, length):
+		self.reached = Signal()
+		###
+		value = Signal(max=length)
+		self.sync += If(~self.reached, value.eq(value+1))
+		self.comb += self.reached.eq(value == (length-1))
+
+class BufferizeEndpoints(ModuleDecorator):
+	def __init__(self, submodule, *args):
+		ModuleDecorator.__init__(self, submodule)
+
+		endpoints = get_endpoints(submodule)
+		sinks = {}
+		sources = {}
+		for name, endpoint in endpoints.items():
+			if name in args or len(args) == 0:
+				if isinstance(endpoint, Sink):
+					sinks.update({name : endpoint})
+				elif isinstance(endpoint, Source):
+					sources.update({name : endpoint})
+
+		# add buffer on sinks
+		for name, sink in sinks.items():
+			buf = Buffer(sink.description)
+			self.submodules += buf
+			setattr(self, name, buf.d)
+			self.comb += Record.connect(buf.q, sink)
+
+		# add buffer on sources
+		for name, source in sources.items():
+			buf = Buffer(source.description)
+			self.submodules += buf
+			self.comb += Record.connect(source, buf.d)
+			setattr(self, name, buf.q)
+
+class EndpointPacketStatus(Module):
+	def __init__(self, endpoint):
+		self.start = Signal()
+		self.done = Signal()
+		self.ongoing = Signal()
+
+		ongoing = Signal()
+		self.comb += [
+			self.start.eq(endpoint.stb & endpoint.sop & endpoint.ack),
+			self.done.eq(endpoint.stb & endpoint.eop & endpoint.ack)
+		]
+		self.sync += \
+			If(self.start,
+				ongoing.eq(1)
+			).Elif(self.done,
+				ongoing.eq(0)
+			)
+		self.comb += self.ongoing.eq((self.start | ongoing) & ~self.done)
+
+class PacketBuffer(Module):
+	def __init__(self, description, data_depth, cmd_depth=4, almost_full=None):
+		self.sink = sink = Sink(description)
+		self.source = source = Source(description)
+
+		###
+		sink_status = EndpointPacketStatus(self.sink)
+		source_status = EndpointPacketStatus(self.source)
+		self.submodules += sink_status, source_status
+
+		# store incoming packets
+		# cmds
+		def cmd_description():
+			layout = [("error", 1)]
+			return EndpointDescription(layout)
+		cmd_fifo = SyncFIFO(cmd_description(), cmd_depth)
+		self.submodules += cmd_fifo
+		self.comb += cmd_fifo.sink.stb.eq(sink_status.done)
+		if hasattr(sink, "error"):
+			self.comb += cmd_fifo.sink.error.eq(sink.error)
+
+		# data
+		data_fifo = SyncFIFO(description, data_depth, buffered=True)
+		self.submodules += data_fifo
+		self.comb += [
+			Record.connect(self.sink, data_fifo.sink),
+			data_fifo.sink.stb.eq(self.sink.stb & cmd_fifo.sink.ack),
+			self.sink.ack.eq(data_fifo.sink.ack & cmd_fifo.sink.ack),
+		]
+
+		# output packets
+		self.fsm = fsm = FSM(reset_state="IDLE")
+		self.submodules += fsm
+		fsm.act("IDLE",
+			If(cmd_fifo.source.stb,
+				NextState("SEEK_SOP")
+			)
+		)
+		fsm.act("SEEK_SOP",
+			If(~data_fifo.source.sop,
+				data_fifo.source.ack.eq(1)
+			).Else(
+				NextState("OUTPUT")
+			)
+		)
+		if hasattr(source, "error"):
+			source_error = self.source.error
+		else:
+			source_error = Signal()
+
+		fsm.act("OUTPUT",
+			Record.connect(data_fifo.source, self.source),
+			source_error.eq(cmd_fifo.source.error),
+			If(source_status.done,
+				cmd_fifo.source.ack.eq(1),
+				NextState("IDLE")
+			)
+		)
+
+		# compute almost full
+		if almost_full is not None:
+			self.almost_full = Signal()
+			self.comb += self.almost_full.eq(data_fifo.fifo.level > almost_full)
diff --git a/liteeth/generic/crossbar.py b/liteeth/generic/crossbar.py
index 4f897856..b60da949 100644
--- a/liteeth/generic/crossbar.py
+++ b/liteeth/generic/crossbar.py
@@ -1,6 +1,7 @@
 from collections import OrderedDict
 
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.arbiter import Arbiter
 from liteeth.generic.dispatcher import Dispatcher
 
diff --git a/liteeth/generic/depacketizer.py b/liteeth/generic/depacketizer.py
index fb1a1b39..2d8ca86c 100644
--- a/liteeth/generic/depacketizer.py
+++ b/liteeth/generic/depacketizer.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 def _decode_header(h_dict, h_signal, obj):
 	r = []
diff --git a/liteeth/generic/packetizer.py b/liteeth/generic/packetizer.py
index 627bb63d..d15b8515 100644
--- a/liteeth/generic/packetizer.py
+++ b/liteeth/generic/packetizer.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 def _encode_header(h_dict, h_signal, obj):
 	r = []
diff --git a/liteeth/mac/__init__.py b/liteeth/mac/__init__.py
index 2346584e..5e88646b 100644
--- a/liteeth/mac/__init__.py
+++ b/liteeth/mac/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.common import *
 from liteeth.mac.core import LiteEthMACCore
 from liteeth.mac.frontend.wishbone import LiteEthMACWishboneInterface
diff --git a/liteeth/mac/common.py b/liteeth/mac/common.py
index 128d8f17..3a68c632 100644
--- a/liteeth/mac/common.py
+++ b/liteeth/mac/common.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.generic.depacketizer import LiteEthDepacketizer
 from liteeth.generic.packetizer import LiteEthPacketizer
 from liteeth.generic.crossbar import LiteEthCrossbar
diff --git a/liteeth/mac/core/__init__.py b/liteeth/mac/core/__init__.py
index 9baa0c9f..d5bf2f93 100644
--- a/liteeth/mac/core/__init__.py
+++ b/liteeth/mac/core/__init__.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.core import gap, preamble, crc, last_be
 
 class LiteEthMACCore(Module, AutoCSR):
diff --git a/liteeth/mac/core/crc.py b/liteeth/mac/core/crc.py
index b14d0a12..80321e4c 100644
--- a/liteeth/mac/core/crc.py
+++ b/liteeth/mac/core/crc.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACCRCEngine(Module):
 	"""Cyclic Redundancy Check Engine
diff --git a/liteeth/mac/core/gap.py b/liteeth/mac/core/gap.py
index 0f1ddd79..84f738aa 100644
--- a/liteeth/mac/core/gap.py
+++ b/liteeth/mac/core/gap.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACGap(Module):
 	def __init__(self, dw, ack_on_gap=False):
diff --git a/liteeth/mac/core/last_be.py b/liteeth/mac/core/last_be.py
index 7d82b934..2b67ad45 100644
--- a/liteeth/mac/core/last_be.py
+++ b/liteeth/mac/core/last_be.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACTXLastBE(Module):
 	def __init__(self, dw):
diff --git a/liteeth/mac/core/preamble.py b/liteeth/mac/core/preamble.py
index 1b9f033c..fd3cb975 100644
--- a/liteeth/mac/core/preamble.py
+++ b/liteeth/mac/core/preamble.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthMACPreambleInserter(Module):
 	def __init__(self, dw):
diff --git a/liteeth/mac/frontend/sram.py b/liteeth/mac/frontend/sram.py
index eefb9a62..cffe71b4 100644
--- a/liteeth/mac/frontend/sram.py
+++ b/liteeth/mac/frontend/sram.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 from migen.bank.description import *
 from migen.bank.eventmanager import *
diff --git a/liteeth/mac/frontend/wishbone.py b/liteeth/mac/frontend/wishbone.py
index 71b467df..a68fe382 100644
--- a/liteeth/mac/frontend/wishbone.py
+++ b/liteeth/mac/frontend/wishbone.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 from liteeth.mac.frontend import sram
 
 from migen.bus import wishbone
diff --git a/liteeth/phy/gmii.py b/liteeth/phy/gmii.py
index 1388704b..180f7da5 100644
--- a/liteeth/phy/gmii.py
+++ b/liteeth/phy/gmii.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYGMIITX(Module):
 	def __init__(self, pads):
diff --git a/liteeth/phy/loopback.py b/liteeth/phy/loopback.py
index 3f5ccf0a..89ffcb3a 100644
--- a/liteeth/phy/loopback.py
+++ b/liteeth/phy/loopback.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYLoopbackCRG(Module, AutoCSR):
 	def __init__(self):
diff --git a/liteeth/phy/mii.py b/liteeth/phy/mii.py
index 1dfda43a..0d3f61be 100644
--- a/liteeth/phy/mii.py
+++ b/liteeth/phy/mii.py
@@ -1,4 +1,5 @@
 from liteeth.common import *
+from liteeth.generic import *
 
 class LiteEthPHYMIITX(Module):
 	def __init__(self, pads):