From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 7 Jan 2022 16:57:56 +0000 (+0000)
Subject: add missing MSRSpec import
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b8febca18a619a34ddd631353fefa7cc563fd34a;p=soc.git

add missing MSRSpec import
---

diff --git a/src/soc/experiment/test/test_ldst_pi.py b/src/soc/experiment/test/test_ldst_pi.py
index fa7bc660..003edf12 100644
--- a/src/soc/experiment/test/test_ldst_pi.py
+++ b/src/soc/experiment/test/test_ldst_pi.py
@@ -27,6 +27,8 @@ from soc.fu.ldst.loadstore import LoadStore1
 from soc.experiment.mmu import MMU
 
 from nmigen.compat.sim import run_simulation
+from openpower.decoder.power_enums import MSRSpec
+
 
 msr_default = MSRSpec(pr=1, dr=0, sf=1) # 64 bit by default