From: Michael Neuling <mikey@neuling.org>
Date: Fri, 19 Jun 2020 01:50:47 +0000 (+1000)
Subject: Merge pull request #208 from paulusmack/faster
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b90a0a2139df87ff16e2d8f085068ee95f4a1f15;p=microwatt.git

Merge pull request #208 from paulusmack/faster

Make the core go faster

Several major improvements in here:
- Simple branch predictor
- Reduced latency for mispredicted branches and interrupts by removing fetch2 stage
- Cache improvements
  o Request critical dword first on refill
  o Handle hits while refilling, including on line being refilled
  o Sizes doubled for both D and I
- Loadstore improvements: can now do one load or store every two cycles in most cases
- Optimized 2-cycle multiplier for Xilinx 7-series parts using DSP slices
- Timing improvements, including:
  o Stash buffer in decode1
  o Reduced width of execute1 result mux
  o Improved SPR decode in decode1
  o Some non-critical operation take a cycle longer so we can break some long combinatorial chains
- Core logging: logs 256 bits of info every cycle into a ring buffer, to help with debugging and performance analysis

This increases the LUT usage for the "synth" + A35 target from 9182 to 10297 = 12%.
---

b90a0a2139df87ff16e2d8f085068ee95f4a1f15