From: Tobias Platen Date: Sun, 27 Mar 2022 17:33:39 +0000 (+0200) Subject: more work on verilator backport X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9186b8d735f468e75ad8487a73c5e0048c39d81;p=microwatt.git more work on verilator backport --- diff --git a/Makefile b/Makefile index 9befa3b..395cc5e 100644 --- a/Makefile +++ b/Makefile @@ -1,3 +1,5 @@ +# merge conflict at + GHDL ?= ghdl GHDLFLAGS=--std=08 CFLAGS=-O3 -Wall @@ -267,6 +269,11 @@ microwatt-verilator-broken: microwatt.v verilator/microwatt-verilator.cpp verila $(VERILATOR) $(VERILATOR_FLAGS) -CFLAGS "$(VERILATOR_CFLAGS) -DCLK_FREQUENCY=$(CLK_FREQUENCY)" -Iuart16550 --assert --cc --exe --build $^ -o $@ -top-module toplevel @cp -f obj_dir/microwatt-verilator microwatt-verilator + +#MEMORY_SIZE=16777216 # 268435456 +#RAM_INIT_FILE=dtbImage.microwatt.hex +SIM_MAIN_BRAM=true + # Need to investigate why yosys is hitting verilator warnings, and eventually turn on -Wall # --top-module toplevel microwatt-verilator: microwatt.v verilator/microwatt-verilator.cpp verilator/uart-verilator.c diff --git a/fpga/top-generic.vhdl b/fpga/top-generic.vhdl index da42bb5..b0005ae 100644 --- a/fpga/top-generic.vhdl +++ b/fpga/top-generic.vhdl @@ -3,12 +3,14 @@ use ieee.std_logic_1164.all; library work; use work.wishbone_types.all; +use work.utils.all; entity toplevel is generic ( MEMORY_SIZE : positive := (384*1024); RAM_INIT_FILE : string := "firmware.hex"; RESET_LOW : boolean := true; + SIM_MAIN_BRAM : boolean := false; CLK_INPUT : positive := 100000000; CLK_FREQUENCY : positive := 100000000; HAS_FPU : boolean := true; @@ -25,7 +27,15 @@ entity toplevel is -- UART0 signals: uart0_txd : out std_ulogic; - uart0_rxd : in std_ulogic + uart0_rxd : in std_ulogic; + + -- BRAM verilator access + bram_we : out std_ulogic; + bram_re : out std_ulogic; + bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); + bram_di : inout std_logic_vector(63 downto 0); + bram_do : out std_logic_vector(63 downto 0); + bram_sel : out std_logic_vector(7 downto 0) ); end entity toplevel; @@ -70,6 +80,7 @@ begin soc0: entity work.soc generic map( MEMORY_SIZE => MEMORY_SIZE, + SIM_MAIN_BRAM => SIM_MAIN_BRAM, RAM_INIT_FILE => RAM_INIT_FILE, SIM => false, CLK_FREQ => CLK_FREQUENCY, @@ -85,7 +96,13 @@ begin system_clk => system_clk, rst => soc_rst, uart0_txd => uart0_txd, - uart0_rxd => uart0_rxd + uart0_rxd => uart0_rxd, + bram_we => bram_we, + bram_re => bram_re, + bram_addr => bram_addr, + bram_di => bram_di, + bram_do => bram_do, + bram_sel => bram_sel ); end architecture behaviour; diff --git a/soc.vhdl b/soc.vhdl index c0c9473..5f35596 100644 --- a/soc.vhdl +++ b/soc.vhdl @@ -7,6 +7,7 @@ use std.env.stop; library work; use work.common.all; +use work.utils.all; use work.wishbone_types.all; @@ -65,6 +66,7 @@ entity soc is DISABLE_FLATTEN_CORE : boolean := false; ALT_RESET_ADDRESS : std_logic_vector(63 downto 0) := (23 downto 0 => '0', others => '1'); HAS_DRAM : boolean := false; + SIM_MAIN_BRAM : boolean := false; DRAM_SIZE : integer := 0; DRAM_INIT_SIZE : integer := 0; HAS_SPI_FLASH : boolean := false; @@ -114,6 +116,14 @@ entity soc is ext_irq_eth : in std_ulogic := '0'; ext_irq_sdcard : in std_ulogic := '0'; + -- BRAM verilator access + bram_we : out std_ulogic; + bram_re : out std_ulogic; + bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); + bram_di : inout std_logic_vector(63 downto 0); + bram_do : out std_logic_vector(63 downto 0); + bram_sel : out std_logic_vector(7 downto 0); + -- UART0 signals: uart0_txd : out std_ulogic; uart0_rxd : in std_ulogic := '0'; @@ -1066,13 +1076,20 @@ begin bram0: entity work.wishbone_bram_wrapper generic map( MEMORY_SIZE => MEMORY_SIZE, - RAM_INIT_FILE => RAM_INIT_FILE + RAM_INIT_FILE => RAM_INIT_FILE, + SIM_MAIN_BRAM => SIM_MAIN_BRAM ) port map( clk => system_clk, rst => rst_bram, wishbone_in => wb_bram_in, - wishbone_out => wb_bram_out + wishbone_out => wb_bram_out, + bram_we => bram_we, + bram_re => bram_re, + bram_addr => bram_addr, + bram_di => bram_di, + bram_do => bram_do, + bram_sel => bram_sel ); end generate; diff --git a/verilator/microwatt-verilator.cpp b/verilator/microwatt-verilator.cpp index a226393..3c4cb07 100644 --- a/verilator/microwatt-verilator.cpp +++ b/verilator/microwatt-verilator.cpp @@ -125,7 +125,8 @@ static void mem_write(unsigned char *mem, } } -#define BRAM_DEBUG +//#define BRAM_DEBUG +//GUESS: signals missing // sigh yes, all these should be runtime commandline options #define TRIGGER_ENABLE @@ -295,6 +296,7 @@ int main(int argc, char **argv) tick(top, traceme); // read/write the memory to/from the mmap'd file (if given) + #warning this us untested if (mem != NULL) { top->bram_do = bram_do; if (top->bram_re ) { @@ -304,7 +306,7 @@ int main(int argc, char **argv) mem_write(mem, top->bram_addr, top->bram_di, top->bram_sel); } } - + uart_tx(top->uart0_txd); top->uart0_rxd = uart_rx(); diff --git a/wishbone_bram_wrapper.vhdl b/wishbone_bram_wrapper.vhdl index a45790f..51a4467 100644 --- a/wishbone_bram_wrapper.vhdl +++ b/wishbone_bram_wrapper.vhdl @@ -11,7 +11,8 @@ use work.wishbone_types.all; entity wishbone_bram_wrapper is generic( MEMORY_SIZE : natural := 4096; --! Memory size in bytes. - RAM_INIT_FILE : string + RAM_INIT_FILE : string; + SIM_MAIN_BRAM : boolean := false ); port( clk : in std_logic; @@ -19,7 +20,16 @@ entity wishbone_bram_wrapper is -- Wishbone interface: wishbone_in : in wishbone_master_out; - wishbone_out : out wishbone_slave_out + wishbone_out : out wishbone_slave_out; + + -- BRAM verilator access + bram_we : out std_ulogic; + bram_re : out std_ulogic; + bram_addr : out std_logic_vector(log2ceil(MEMORY_SIZE) - 3- 1 downto 0); + bram_di : inout std_logic_vector(63 downto 0); + bram_do : out std_logic_vector(63 downto 0); + bram_sel : out std_logic_vector(7 downto 0) + ); end entity wishbone_bram_wrapper;