From: Luke Kenneth Casson Leighton Date: Tue, 2 May 2023 17:52:14 +0000 (+0100) Subject: update comments and correct retiring, remove registers that have been written X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b91ea4b2eadeb733a776394f995fe0668afb09ed;p=openpower-isa.git update comments and correct retiring, remove registers that have been written --- diff --git a/src/openpower/cyclemodel/inorder.py b/src/openpower/cyclemodel/inorder.py index 42176990..5d311c69 100644 --- a/src/openpower/cyclemodel/inorder.py +++ b/src/openpower/cyclemodel/inorder.py @@ -2,11 +2,22 @@ # An In-order cycle-accurate model of a Power ISA 3.0 hardware implementation class RegisterWrite(set): + """RegisterWrite: contains the set of Read-after-Write Hazards. + Anything in this set must be a STALL at Decode phase because the + answer has still not popped out the end of a pipeline + """ def expect_write(self, regs): self.update(regs) def write_expected(self, regs): len(self.intersection(regs)) != 0 def retire_write(self, regs): self.difference_update(regs) class Execute: + """Execute Pipeline: keeps a countdown-sorted list of instructions + to expect at a future cycle (tick). Anything at zero is processed + by assuming it is completed, and wishes to write to the regfile. + However there are only a limited number of regfile write ports, + so they must be handled a few at a time. under these circumstances + STALL condition is returned, and the "processor" must *NOT* tick(). + """ def __init__(self, cpu): self.stages = [] self.cpu = cpu @@ -33,5 +44,8 @@ class Execute: if writes_possible != to_write: stall = True # retire the writes that are possible in this cycle (regfile writes) - self.cpu.regs.retire_write(to_write) + self.cpu.regs.retire_write(writes_possible) + # and now go through the instructions, removing those regs written + for instruction in instructions: + instruction['writes'].difference_update(writes_possible) return stall