From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sun, 28 Jul 2019 08:52:04 +0000 (+0100)
Subject: add debugging fclass
X-Git-Tag: ls180-24jan2020~719
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b927d5b6ecc130bd9a375be01d32140da79edd22;p=ieee754fpu.git

add debugging fclass
---

diff --git a/src/ieee754/fclass/pipeline.py b/src/ieee754/fclass/pipeline.py
index 638d05c4..348b8234 100644
--- a/src/ieee754/fclass/pipeline.py
+++ b/src/ieee754/fclass/pipeline.py
@@ -75,7 +75,7 @@ class FPClassMod(Elaboratable):
         m.d.comb += finite_nzero.eq(~a1.is_nan & ~a1.is_inf & ~a1.is_zero)
         subnormal = a1.exp_lt_n126
 
-        m.d.comb += self.o.z.eqCat(
+        m.d.comb += self.o.z.eq(Cat(
                     a1.s   & a1.is_inf,                 # | −inf.
                     a1.s   & finite_nzero & ~subnormal, # | -normal number.
                     a1.s   & finite_nzero &  subnormal, # | -subnormal number.
@@ -85,7 +85,7 @@ class FPClassMod(Elaboratable):
                     ~a1.s & finite_nzero & ~subnormal,  # | +normal number.
                     ~a1.s & a1.is_inf,                  # | +inf.
                     a1.is_denormalised,                 # | a signaling NaN.
-                    a1.is_nan & ~a1.is_denormalised)    # | a quiet NaN
+                    a1.is_nan & ~a1.is_denormalised))   # | a quiet NaN
 
         m.d.comb += self.o.ctx.eq(self.i.ctx)
 
diff --git a/src/ieee754/fclass/test/test_fclass_pipe.py b/src/ieee754/fclass/test/test_fclass_pipe.py
new file mode 100644
index 00000000..ec239c4d
--- /dev/null
+++ b/src/ieee754/fclass/test/test_fclass_pipe.py
@@ -0,0 +1,52 @@
+""" test of FPClassMuxInOut
+"""
+
+from ieee754.fclass.pipeline import (FPClassMuxInOut,)
+from ieee754.fpcommon.test.fpmux import runfp
+from ieee754.fpcommon.fpbase import FPFormat
+
+import sfpy
+from sfpy import Float64, Float32, Float16
+
+def fclass(wid, x):
+    x = x.bits
+    fmt = FPFormat.standard(wid)
+    if fmt.is_inf(x):
+        if fmt.get_sign(x):
+            return 1<<0
+        else:
+            return 1<<7
+    if fmt.is_zero(x):
+        if fmt.get_sign(x):
+            return 1<<3
+        else:
+            return 1<<4
+    if fmt.get_exponent(x) == fmt.emax:
+        if fmt.is_nan_signalling(x):
+            return 1<<8
+        else:
+            return 1<<9
+    if fmt.is_subnormal(x) and fmt.get_mantissa(x) != 0:
+        if fmt.get_sign(x):
+            return 1<<2
+        else:
+            return 1<<5
+    if fmt.get_sign(x):
+        return 1<<1
+    else:
+        return 1<<6
+
+
+def fclass_16(x):
+    return fclass(16, x)
+
+
+def test_class_pipe_f16():
+    dut = FPClassMuxInOut(16, 16, 4, op_wid=1)
+    runfp(dut, 16, "test_fcvt_class_pipe_f16", Float16, fclass_16,
+                True, n_vals=100)
+
+
+if __name__ == '__main__':
+    for i in range(200):
+        test_class_pipe_f16()
diff --git a/src/ieee754/fpcommon/fpbase.py b/src/ieee754/fpcommon/fpbase.py
index 2413a365..ef2a065c 100644
--- a/src/ieee754/fpcommon/fpbase.py
+++ b/src/ieee754/fpcommon/fpbase.py
@@ -102,14 +102,12 @@ class FPFormat:
         """ returns true if x is subnormal (exp at minimum
         """
         e_sub = self.exponent_denormal_zero - self.exponent_bias
-        print ("e_sub", e_sub)
         return self.get_exponent(x) == e_sub and self.get_mantissa(x) == 0
 
     def is_subnormal(self, x):
         """ returns true if x is subnormal (exp at minimum
         """
         e_sub = self.exponent_denormal_zero - self.exponent_bias
-        print ("e_sub", e_sub)
         return self.get_exponent(x) == e_sub and self.get_mantissa(x) != 0
 
     def is_inf(self, x):