From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Tue, 24 Apr 2018 12:49:39 +0000 (+0100)
Subject: clarify
X-Git-Tag: convert-csv-opcode-to-binary~5576
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b928ad938fa030928f1da4d5598bcf4709e7749a;p=libreriscv.git

clarify
---

diff --git a/simple_v_extension.mdwn b/simple_v_extension.mdwn
index b9f94b3fc..dc35f6cfa 100644
--- a/simple_v_extension.mdwn
+++ b/simple_v_extension.mdwn
@@ -1047,7 +1047,7 @@ the question is asked "How can each of the proposals effectively implement
   a SIMD architecture where the ALU becomes responsible for the parallelism,
   Alt-RVP ALUs would likewise be so responsible... with *additional*
   (lane-based) parallelism on top.
-* Thus at least some of the downsides of SIMD ISA O(N^3) proliferation by
+* Thus at least some of the downsides of SIMD ISA O(N^5) proliferation by
   at least one dimension are avoided (architectural upgrades introducing
   128-bit then 256-bit then 512-bit variants of the exact same 64-bit
   SIMD block)