From: Clifford Wolf <clifford@clifford.at>
Date: Wed, 4 Oct 2017 15:23:42 +0000 (+0200)
Subject: Fix nasty bug in Verific bindings
X-Git-Tag: yosys-0.8~304
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b92ff2706e0ad3b57d7cab06528f9c1287ef81fc;p=yosys.git

Fix nasty bug in Verific bindings
---

diff --git a/frontends/verific/verific.cc b/frontends/verific/verific.cc
index 83fe61c18..71e07f670 100644
--- a/frontends/verific/verific.cc
+++ b/frontends/verific/verific.cc
@@ -912,7 +912,7 @@ struct VerificImporter
 
 			if (found_new_net)
 			{
-				RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(net->Name()) : NEW_ID);
+				RTLIL::IdString wire_name = module->uniquify(mode_names || netbus->IsUserDeclared() ? RTLIL::escape_id(netbus->Name()) : NEW_ID);
 
 				if (verbose)
 					log("  importing netbus %s as %s.\n", netbus->Name(), log_id(wire_name));