From: lkcl <lkcl@web>
Date: Sat, 2 Oct 2021 22:42:32 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls005_v1~3750
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b930fba117b96db0297f3166a4016c462a90a49d;p=libreriscv.git

---

diff --git a/3d_gpu/architecture/dynamic_simd.mdwn b/3d_gpu/architecture/dynamic_simd.mdwn
index f433db9ce..14c18c1c3 100644
--- a/3d_gpu/architecture/dynamic_simd.mdwn
+++ b/3d_gpu/architecture/dynamic_simd.mdwn
@@ -9,6 +9,35 @@
 * <https://bugs.libre-soc.org/show_bug.cgi?id=596> Formal proof of PartitionedSignal nmigen interaction
 * <https://bugs.libre-soc.org/show_bug.cgi?id=713> Partition-context-sensitive length adjustment
 
+# Proposal Summary
+
+The proposal is two-fold, and targetted at the two distinct types
+of nmigen language constructs:
+
+* Type 1 low-level AST.  implemented as nmigen.hdl.ast classes
+* Type 2 high-level DSL. Implemented as Module in nmigen.hdl.dsl
+
+The Type 1 AST low-level proposed modifications are mirrored on the
+existing long-established python `operator` module, which nmigen
+*already leverages* by providing `Value.__add__` and other operator
+overrides.
+
+* To extend nmigen "Type 1 (ast.*)" low-level language constructs
+  with `Value.__Cat__`, `Value.__Switch__`, `Value.__Repl__` etc.
+* To rename `ast.Cat` etc to `ast._InternalCat`
+* In an identical conceptual fashion as python `operator.add`
+  to redirect `ast.Cat` to `Value.__Cat__` etc.
+* To have `Value.__Cat__` etc call the now-renamed `ast._InternalCat`
+
+The second set of changes is targetted at Type 2 dsl.Module,
+to complete the 98% abstraction from Type 1 to a 100% level
+
+* To add a new parameter to Module which is the AST class type
+  to be used for "casting" of m.If and m.Elif condition tests,
+  and for m.Switch values
+
+No further modifications beyond that are strictly necessary.
+
 # Rationale / Introduction
 
 The Dynamic Partitioned SIMD Signal is effectively a parallelisation
@@ -124,33 +153,6 @@ basic HDL is literally an order of magnitude larger:
     with m.ElIf(....)
         ....
 
-# Proposal
-
-The proposal is two-fold, and targetted at the two distinct types
-of nmigen language constructs:
-
-* Type 1 low-level AST.  implemented as nmigen.hdl.ast classes
-* Type 2 high-level DSL. Implemented as Module in nmigen.hdl.dsl
-
-The Type 1 AST low-level proposed modifications are mirrored on the
-existing long-established python `operator` module, which nmigen
-*already leverages* by providing `Value.__add__` and other operator
-overrides.
-
-* To extend nmigen "Type 1 (ast.*)" low-level language constructs
-  with `Value.__Cat__`, `Value.__Switch__`, `Value.__Repl__` etc.
-* To rename `ast.Cat` etc to `ast._InternalCat`
-* In an identical conceptual fashion as python `operator.add`
-  to redirect `ast.Cat` to `Value.__Cat__` etc.
-* To have `Value.__Cat__` etc call the now-renamed `ast._InternalCat`
-
-The second set of changes is targetted at Type 2 dsl.Module,
-to complete the 98% abstraction from Type 1 to a 100% level
-
-* To add a new parameter to Module which is the AST class type
-  to be used for "casting" of m.If and m.Elif condition tests,
-  and for m.Switch values
-
 # Overview
 
 To save hugely on gate count the normal practice of having separate scalar ALUs and separate SIMD ALUs is not followed.