From: Florent Kermarrec Date: Fri, 10 Apr 2020 13:50:35 +0000 (+0200) Subject: altera/common: add DDROutput, DDRInput, SDROutput, SDRInput. X-Git-Tag: 24jan2021_ls180~466 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b95e0a19b105751d2868b83e737f767ad90898aa;p=litex.git altera/common: add DDROutput, DDRInput, SDROutput, SDRInput. --- diff --git a/litex/build/altera/common.py b/litex/build/altera/common.py index 252f5fbd..e9adf2a3 100644 --- a/litex/build/altera/common.py +++ b/litex/build/altera/common.py @@ -9,7 +9,35 @@ from migen.genlib.resetsync import AsyncResetSynchronizer from litex.build.io import * -# DifferentialInput -------------------------------------------------------------------------------- +# Common AsyncResetSynchronizer -------------------------------------------------------------------- + +class AlteraAsyncResetSynchronizerImpl(Module): + def __init__(self, cd, async_reset): + rst_meta = Signal() + self.specials += [ + Instance("DFF", + i_d = 0, + i_clk = cd.clk, + i_clrn = 1, + i_prn = ~async_reset, + o_q = rst_meta + ), + Instance("DFF", + i_d = rst_meta, + i_clk = cd.clk, + i_clrn = 1, + i_prn = ~async_reset, + o_q = cd.rst + ) + ] + + +class AlteraAsyncResetSynchronizer: + @staticmethod + def lower(dr): + return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) + +# Common DifferentialInput ------------------------------------------------------------------------- class AlteraDifferentialInputImpl(Module): def __init__(self, i_p, i_n, o): @@ -28,7 +56,7 @@ class AlteraDifferentialInput: def lower(dr): return AlteraDifferentialInputImpl(dr.i_p, dr.i_n, dr.o) -# DifferentialOutput ------------------------------------------------------------------------------- +# Common DifferentialOutput ------------------------------------------------------------------------ class AlteraDifferentialOutputImpl(Module): def __init__(self, i, o_p, o_n): @@ -47,38 +75,63 @@ class AlteraDifferentialOutput: def lower(dr): return AlteraDifferentialOutputImpl(dr.i, dr.o_p, dr.o_n) -# AsyncResetSynchronizer --------------------------------------------------------------------------- +# Common DDROutput --------------------------------------------------------------------------------- -class AlteraAsyncResetSynchronizerImpl(Module): - def __init__(self, cd, async_reset): - rst_meta = Signal() - self.specials += [ - Instance("DFF", - i_d = 0, - i_clk = cd.clk, - i_clrn = 1, - i_prn = ~async_reset, - o_q = rst_meta - ), - Instance("DFF", - i_d = rst_meta, - i_clk = cd.clk, - i_clrn = 1, - i_prn = ~async_reset, - o_q = cd.rst - ) - ] +class AlteraDDROutputImpl(Module): + def __init__(self, i1, i2, o, clk): + self.specials += Instance("ALTDDIO_OUT", + p_WIDTH = 1, + i_outclock = clk, + i_datain_h = i1, + i_datain_l = i2, + o_dataout = o, + ) -class AlteraAsyncResetSynchronizer: +class AlteraDDROutput: @staticmethod def lower(dr): - return AlteraAsyncResetSynchronizerImpl(dr.cd, dr.async_reset) + return AlteraDDROutputImpl(dr.i1, dr.i2, dr.o, dr.clk) + +# Common DDRInput ---------------------------------------------------------------------------------- + +class AlteraDDRInputImpl(Module): + def __init__(self, i, o1, o2, clk): + self.specials += Instance("ALTDDIO_IN", + p_WIDTH = 1, + i_inclock = clk, + i_datain = i, + o_dataout_h = o1, + o_dataout_l = o2 + ) + +class AlteraDDRInput: + @staticmethod + def lower(dr): + return AlteraDDRInputImpl(dr.i, dr.o1, dr.o2, dr.clk) + +# Common SDROutput ------------------------------------------------------------------------------- + +class AlteraSDROutput: + @staticmethod + def lower(dr): + return AlteraDDROutputImpl(dr.i, dr.i, dr.o, dr.clk) + +# Common SDRInput -------------------------------------------------------------------------------- + +class AlteraSDRInput: + @staticmethod + def lower(dr): + return AlteraDDRInputImpl(dr.i, dr.o, Signal(), dr.clk) # Special Overrides -------------------------------------------------------------------------------- altera_special_overrides = { + AsyncResetSynchronizer: AlteraAsyncResetSynchronizer, DifferentialInput: AlteraDifferentialInput, DifferentialOutput: AlteraDifferentialOutput, - AsyncResetSynchronizer: AlteraAsyncResetSynchronizer, + DDROutput: AlteraDDROutput, + DDRInput: AlteraDDRInput, + SDROutput: AlteraSDROutput, + SDRInput: AlteraSDRInput, }