From: Eddie Hung <eddie@fpgeh.com>
Date: Wed, 11 Dec 2019 19:49:13 +0000 (-0800)
Subject: Supress error for unhandled \init if whole module selected
X-Git-Tag: working-ls180~663^2~7
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b97a9cd3f3619f035af4792de199298487c689a9;p=yosys.git

Supress error for unhandled \init if whole module selected
---

diff --git a/passes/techmap/zinit.cc b/passes/techmap/zinit.cc
index a427c4987..5cfc82ac9 100644
--- a/passes/techmap/zinit.cc
+++ b/passes/techmap/zinit.cc
@@ -141,9 +141,10 @@ struct ZinitPass : public Pass {
 				cell->setPort(ID::Q, initwire);
 			}
 
-			for (auto &it : initbits)
-				if (donebits.count(it.first) == 0)
-					log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
+			if (!design->selected_whole_module(module))
+				for (auto &it : initbits)
+					if (donebits.count(it.first) == 0)
+						log_error("Failed to handle init bit %s = %s.\n", log_signal(it.first), log_signal(it.second));
 		}
 	}
 } ZinitPass;