From: Jacob Lifshay Date: Mon, 26 Sep 2022 21:57:12 +0000 (-0700) Subject: pcdec. max bits handled for 1 code is 5 bits, not 6 X-Git-Tag: opf_rfc_ls005_v1~278 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b97b508bfe2d8be265e7ec637a9dea19c5e83625;p=libreriscv.git pcdec. max bits handled for 1 code is 5 bits, not 6 --- diff --git a/openpower/prefix_codes.mdwn b/openpower/prefix_codes.mdwn index 24a993b52..71119b6f6 100644 --- a/openpower/prefix_codes.mdwn +++ b/openpower/prefix_codes.mdwn @@ -48,7 +48,7 @@ t[8] t[9] t[10] t[11] t[12] t[13] t[14] t[15] and so on for t[16..] ``` -Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RA in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >6-bits, so SO/OV/OV32 are set, and decoding stops. +Decoding a code word works by walking on the tree from the root to the children, matching each passed 0 or 1 to the next read input bit in RA in LSB to MSB order. When `t[i]` is set, then a valid code word was read and `i` is written to the next byte of output in RT in LSB to MSB order. When no set `t[i]` is encountered, and there are still input bits left, then the code word is >5-bits, so SO/OV/OV32 are set, and decoding stops. [[!inline pages="openpower/isa/prefix_codes" quick="yes" raw="yes" ]]