From: Clifford Wolf Date: Sat, 9 Aug 2014 13:17:54 +0000 (+0200) Subject: Do not share any $reduce_* cells (its complicated and not worth it anyways) X-Git-Tag: yosys-0.4~285 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9811d5aff7ca31daa214386a041af0865813813;p=yosys.git Do not share any $reduce_* cells (its complicated and not worth it anyways) --- diff --git a/passes/sat/share.cc b/passes/sat/share.cc index 7141cea2a..065b90d3e 100644 --- a/passes/sat/share.cc +++ b/passes/sat/share.cc @@ -252,19 +252,6 @@ struct ShareWorker if (config.generic_uni_ops.count(c1->type)) { - if (c1->type.in("$reduce_and", "$reduce_or", "$reduce_xor", "$reduce_xnor", "$reduce_bool") && c1->getParam("\\A_WIDTH").as_int() != c2->getParam("\\A_WIDTH").as_int()) - { - RTLIL::SigBit extbit = c1->type == "$reduce_and" ? RTLIL::State::S1 : RTLIL::State::S0; - while (c1->getParam("\\A_WIDTH").as_int() < c2->getParam("\\A_WIDTH").as_int()) { - c1->setParam("\\A_WIDTH", c1->getParam("\\A_WIDTH").as_int() + 1); - c1->setPort("\\A", {extbit, c1->getPort("\\A")}); - } - while (c2->getParam("\\A_WIDTH").as_int() < c1->getParam("\\A_WIDTH").as_int()) { - c2->setParam("\\A_WIDTH", c2->getParam("\\A_WIDTH").as_int() + 1); - c2->setPort("\\A", {extbit, c2->getPort("\\A")}); - } - } - if (c1->parameters.at("\\A_SIGNED").as_bool() != c2->parameters.at("\\A_SIGNED").as_bool()) { RTLIL::Cell *unsigned_cell = c1->parameters.at("\\A_SIGNED").as_bool() ? c2 : c1; @@ -923,12 +910,6 @@ struct SharePass : public Pass { // config.generic_uni_ops.insert("$bu0"); config.generic_uni_ops.insert("$neg"); - config.generic_uni_ops.insert("$reduce_and"); - config.generic_uni_ops.insert("$reduce_or"); - config.generic_uni_ops.insert("$reduce_xor"); - config.generic_uni_ops.insert("$reduce_xnor"); - config.generic_uni_ops.insert("$reduce_bool"); - config.generic_cbin_ops.insert("$and"); config.generic_cbin_ops.insert("$or"); config.generic_cbin_ops.insert("$xor");