From: lkcl <lkcl@web>
Date: Fri, 8 Jan 2021 14:06:46 +0000 (+0000)
Subject: (no commit message)
X-Git-Tag: convert-csv-opcode-to-binary~556
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b981c6e582a43f7a1102dd4ca1f4f3b6ccc0ccc3;p=libreriscv.git

---

diff --git a/openpower/sv.mdwn b/openpower/sv.mdwn
index e8b72d884..7595ce738 100644
--- a/openpower/sv.mdwn
+++ b/openpower/sv.mdwn
@@ -43,8 +43,8 @@ Pages being developed and examples
 * [[sv/cr_int_predication]]
 * [[sv/setvl]]
 * [[sv/svp64]]
-* [[sv/ldst]]
-* [[sv/sprs]]
+* [[sv/ldst]] Load and Store
+* [[sv/sprs]] SPRs
 * [[sv/bitmanip]]
 * [[sv/propagation]] Context propagation including svp64, swizzle and remap
 * [[sv/vector_ops]] Vector ops needed to make a "complete" Vector ISA