From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 3 Dec 2020 15:51:56 +0000 (+0000)
Subject: argh issue with yosys ABC
X-Git-Tag: 24jan2021_ls180~76
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9821fff0ab14483f5d1373ea7ca106e01436e91;p=soc.git

argh issue with yosys ABC
---

diff --git a/src/soc/litex/florent/ls180soc.py b/src/soc/litex/florent/ls180soc.py
index 8566988a..f8c71ebb 100755
--- a/src/soc/litex/florent/ls180soc.py
+++ b/src/soc/litex/florent/ls180soc.py
@@ -339,7 +339,8 @@ class LibreSoCSim(SoCCore):
             sdram_module          = sdram_module,
             sdram_data_width      = sdram_data_width,
             integrated_rom_size      = 0, # if ram_fname else 0x10000,
-            integrated_sram_size     = 0x1000,
+            #integrated_sram_size     = 0x1000, - problem with yosys ABC
+            integrated_sram_size     = 0x200,
             #integrated_main_ram_init  = ram_init,
             integrated_main_ram_size = 0x00000000 if with_sdram \
                                         else 0x10000000 , # 256MB