From: Alexander Ivchenko Date: Wed, 10 Sep 2014 06:54:51 +0000 (+0000) Subject: AVX-512. Add reduce, range, fpclass insn patterns. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9826286455578db4b0a3b8eb511484407745797;p=gcc.git AVX-512. Add reduce, range, fpclass insn patterns. gcc/ * config/i386/i386.c (ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round, avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask, avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask, avx512dq_rangepv4sf_mask. * config/i386/sse.md (define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS, UNSPEC_RANGE. (define_insn "reducep"): New. (define_insn "reduces"): Ditto. (define_insn "avx512dq_rangep"): Ditto. (define_insn "avx512dq_ranges"): Ditto. (define_insn "avx512dq_fpclass"): Ditto. (define_insn "avx512dq_vmfpclass"): Ditto.. Co-Authored-By: Andrey Turetskiy Co-Authored-By: Anna Tikhonova Co-Authored-By: Ilya Tocar Co-Authored-By: Ilya Verbin Co-Authored-By: Kirill Yukhin Co-Authored-By: Maxim Kuznetsov Co-Authored-By: Michael Zolotukhin From-SVN: r215107 --- diff --git a/gcc/ChangeLog b/gcc/ChangeLog index 5145acab20a..7668aab8420 100644 --- a/gcc/ChangeLog +++ b/gcc/ChangeLog @@ -1,3 +1,28 @@ +2014-09-10 Alexander Ivchenko + Maxim Kuznetsov + Anna Tikhonova + Ilya Tocar + Andrey Turetskiy + Ilya Verbin + Kirill Yukhin + Michael Zolotukhin + + * config/i386/i386.c + (ix86_expand_args_builtin): Handle avx512dq_rangepv8df_mask_round, + avx512dq_rangepv16sf_mask_round, avx512dq_rangepv4df_mask, + avx512dq_rangepv8sf_mask, avx512dq_rangepv2df_mask, + avx512dq_rangepv4sf_mask. + * config/i386/sse.md + (define_c_enum "unspec"): Add UNSPEC_REDUCE, UNSPEC_FPCLASS, + UNSPEC_RANGE. + (define_insn "reducep"): New. + (define_insn "reduces"): Ditto. + (define_insn "avx512dq_rangep"): + Ditto. + (define_insn "avx512dq_ranges"): Ditto. + (define_insn "avx512dq_fpclass"): Ditto. + (define_insn "avx512dq_vmfpclass"): Ditto.. + 2014-09-10 Alexander Ivchenko Maxim Kuznetsov Anna Tikhonova diff --git a/gcc/config/i386/i386.c b/gcc/config/i386/i386.c index 844908939df..8f45e52d9f3 100644 --- a/gcc/config/i386/i386.c +++ b/gcc/config/i386/i386.c @@ -34090,6 +34090,12 @@ ix86_expand_args_builtin (const struct builtin_description *d, case CODE_FOR_avx512vl_getmantv4df_mask: case CODE_FOR_avx512vl_getmantv4sf_mask: case CODE_FOR_avx512vl_getmantv2df_mask: + case CODE_FOR_avx512dq_rangepv8df_mask_round: + case CODE_FOR_avx512dq_rangepv16sf_mask_round: + case CODE_FOR_avx512dq_rangepv4df_mask: + case CODE_FOR_avx512dq_rangepv8sf_mask: + case CODE_FOR_avx512dq_rangepv2df_mask: + case CODE_FOR_avx512dq_rangepv4sf_mask: error ("the last argument must be a 4-bit immediate"); return const0_rtx; diff --git a/gcc/config/i386/sse.md b/gcc/config/i386/sse.md index 1706e4ca1ca..78276b79670 100644 --- a/gcc/config/i386/sse.md +++ b/gcc/config/i386/sse.md @@ -128,6 +128,11 @@ UNSPEC_SHA256MSG1 UNSPEC_SHA256MSG2 UNSPEC_SHA256RNDS2 + + ;; For AVX512DQ support + UNSPEC_REDUCE + UNSPEC_FPCLASS + UNSPEC_RANGE ]) (define_c_enum "unspecv" [ @@ -2330,6 +2335,34 @@ DONE; }) +(define_insn "reducep" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "nonimmediate_operand" "vm") + (match_operand:SI 2 "const_0_to_255_operand")] + UNSPEC_REDUCE))] + "TARGET_AVX512DQ" + "vreduce\t{%2, %1, %0|%0, %1, %2}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "reduces" + [(set (match_operand:VF_128 0 "register_operand" "=v") + (vec_merge:VF_128 + (unspec:VF_128 + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:VF_128 2 "nonimmediate_operand" "vm") + (match_operand:SI 3 "const_0_to_255_operand")] + UNSPEC_REDUCE) + (match_dup 1) + (const_int 1)))] + "TARGET_AVX512DQ" + "vreduce\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; ;; ;; Parallel floating point comparisons @@ -16754,6 +16787,63 @@ (set_attr "memory" "none,load") (set_attr "mode" "")]) +(define_insn "avx512dq_rangep" + [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") + (unspec:VF_AVX512VL + [(match_operand:VF_AVX512VL 1 "register_operand" "v") + (match_operand:VF_AVX512VL 2 "" "") + (match_operand:SI 3 "const_0_to_15_operand")] + UNSPEC_RANGE))] + "TARGET_AVX512DQ && " + "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_ranges" + [(set (match_operand:VF_128 0 "register_operand" "=v") + (vec_merge:VF_128 + (unspec:VF_128 + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:VF_128 2 "" "") + (match_operand:SI 3 "const_0_to_15_operand")] + UNSPEC_RANGE) + (match_dup 1) + (const_int 1)))] + "TARGET_AVX512DQ" + "vrange\t{%3, %2, %1, %0|%0, %1, %2, %3}" + [(set_attr "type" "sse") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_fpclass" + [(set (match_operand: 0 "register_operand" "=Yk") + (unspec: + [(match_operand:VF_AVX512VL 1 "register_operand" "v") + (match_operand:QI 2 "const_0_to_255_operand" "n")] + UNSPEC_FPCLASS))] + "TARGET_AVX512DQ" + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + [(set_attr "type" "sse") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + +(define_insn "avx512dq_vmfpclass" + [(set (match_operand: 0 "register_operand" "=Yk") + (and: + (unspec: + [(match_operand:VF_128 1 "register_operand" "v") + (match_operand:QI 2 "const_0_to_255_operand" "n")] + UNSPEC_FPCLASS) + (const_int 1)))] + "TARGET_AVX512DQ" + "vfpclass\t{%2, %1, %0|%0, %1, %2}"; + [(set_attr "type" "sse") + (set_attr "length_immediate" "1") + (set_attr "prefix" "evex") + (set_attr "mode" "")]) + (define_insn "_getmant" [(set (match_operand:VF_AVX512VL 0 "register_operand" "=v") (unspec:VF_AVX512VL