From: Eddie Hung <eddie@fpgeh.com>
Date: Thu, 20 Jun 2019 17:10:43 +0000 (-0700)
Subject: Add test
X-Git-Tag: yosys-0.9~58^2~5
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b98276fa61be7a1c589d6dac661d31982cfab16b;p=yosys.git

Add test
---

diff --git a/tests/various/signext.ys b/tests/various/signext.ys
new file mode 100644
index 000000000..26dab13a6
--- /dev/null
+++ b/tests/various/signext.ys
@@ -0,0 +1,24 @@
+
+read_verilog -formal <<EOT
+module gate(input clk, output [1:0] o);
+assign o = 1'bx;
+endmodule
+EOT
+
+
+## Example usage for "pmuxtree" and "muxcover"
+
+proc
+
+## Equivalence checking
+
+read_verilog -formal <<EOT
+module gold(input clk, output [1:0] o);
+assign o = 2'bxx;
+endmodule
+EOT
+
+proc
+
+miter -equiv -flatten -make_assert -make_outputs gold gate miter
+sat -verify -prove-asserts -show-ports -enable_undef miter