From: Clifford Wolf <clifford@clifford.at>
Date: Sat, 2 Aug 2014 11:11:01 +0000 (+0200)
Subject: More cleanups related to RTLIL::IdString usage
X-Git-Tag: yosys-0.4~331
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9bd22b8c8d46284fba4d4c1cbd09092a9ccc5c3;p=yosys.git

More cleanups related to RTLIL::IdString usage
---

diff --git a/backends/blif/blif.cc b/backends/blif/blif.cc
index b31d6ce6f..ecde8b5a3 100644
--- a/backends/blif/blif.cc
+++ b/backends/blif/blif.cc
@@ -209,7 +209,7 @@ struct BlifDumper
 				continue;
 			}
 
-			fprintf(f, ".%s %s", subckt_or_gate(cell->type), cstr(cell->type));
+			fprintf(f, ".%s %s", subckt_or_gate(cell->type.str()), cstr(cell->type));
 			for (auto &conn : cell->connections())
 			for (int i = 0; i < conn.second.size(); i++) {
 				if (conn.second.size() == 1)
diff --git a/backends/btor/btor.cc b/backends/btor/btor.cc
index d8a542347..201be0cf5 100644
--- a/backends/btor/btor.cc
+++ b/backends/btor/btor.cc
@@ -428,7 +428,7 @@ struct BtorDumper
 				{	
 					cell_line = ++line_num;
 					bool reduced = (cell->type == "$not" || cell->type == "$neg") ? false : true;
-					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type).c_str(), reduced?output_width:w, l);
+					str = stringf ("%d %s %d %d", cell_line, cell_type_translation.at(cell->type.str()).c_str(), reduced?output_width:w, l);
 					fprintf(f, "%s\n", str.c_str());
 				}
 				if(output_width < w && (cell->type == "$not" || cell->type == "$neg" || cell->type == "$pos"))
@@ -487,13 +487,13 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
-				std::string op = cell_type_translation.at(cell->type);
+				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$lt" || cell->type == "$le" ||
 				 cell->type == "$eq" || cell->type == "$ne" || cell->type == "$eqx" || cell->type == "$nex" ||
 				 cell->type == "$ge" || cell->type == "$gt")
 				{
 					if(l1_signed)
-						op = s_cell_type_translation.at(cell->type);
+						op = s_cell_type_translation.at(cell->type.str());
 				}
 				
 				str = stringf ("%d %s %d %d %d", line_num, op.c_str(), output_width, l1, l2);
@@ -521,9 +521,9 @@ struct BtorDumper
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), l2_width);
 				
 				++line_num;
-				std::string op = cell_type_translation.at(cell->type);
+				std::string op = cell_type_translation.at(cell->type.str());
 				if(cell->type == "$div" && l1_signed)
-					op = s_cell_type_translation.at(cell->type);
+					op = s_cell_type_translation.at(cell->type.str());
 				else if(cell->type == "$mod")
 				{
 					if(l1_signed)
@@ -555,7 +555,7 @@ struct BtorDumper
 				int l1 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\A")), l1_width);
 				int l2 = dump_sigspec(&cell->getPort(RTLIL::IdString("\\B")), ceil(log(l1_width)/log(2)));
 				int cell_output = ++line_num;
-				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), l1_width, l1, l2);
+				str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), l1_width, l1, l2);
 				fprintf(f, "%s\n", str.c_str());
 
 				if(l2_width > ceil(log(l1_width)/log(2)))
@@ -635,7 +635,7 @@ struct BtorDumper
 				int s = dump_sigspec(&cell->getPort(RTLIL::IdString("\\S")), 1);
 				++line_num;
 				str = stringf ("%d %s %d %d %d %d", 
-					line_num, cell_type_translation.at(cell->type).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
+					line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, s, l2, l1);//if s is 0 then l1, if s is 1 then l2 //according to the implementation of mux cell
 				fprintf(f, "%s\n", str.c_str());
 				line_ref[cell->name]=line_num;
 			}
@@ -697,7 +697,7 @@ struct BtorDumper
 						fprintf(f, "%s\n", str.c_str());
 					}
 					++line_num;
-					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), 
+					str = stringf ("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), 
 						output_width, reg, next);
 					fprintf(f, "%s\n", str.c_str());
 				}
@@ -768,7 +768,7 @@ struct BtorDumper
 				log_assert(output->size() == output_width);
 				int offset = cell->parameters.at(RTLIL::IdString("\\OFFSET")).as_int();	
 				++line_num;
-				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), output_width, input_line, output_width+offset-1, offset);	
+				str = stringf("%d %s %d %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), output_width, input_line, output_width+offset-1, offset);
 				fprintf(f, "%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;	
 			}
@@ -784,7 +784,7 @@ struct BtorDumper
 				log_assert(input_b->size() == input_b_width);
 				int input_b_line = dump_sigspec(input_b, input_b_width);
 				++line_num;
-				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type).c_str(), input_a_width+input_b_width, 
+				str = stringf("%d %s %d %d %d", line_num, cell_type_translation.at(cell->type.str()).c_str(), input_a_width+input_b_width, 
 					input_a_line, input_b_line);	
 				fprintf(f, "%s\n", str.c_str());				
 				line_ref[cell->name]=line_num;				
@@ -888,7 +888,7 @@ struct BtorDumper
 				inputs[wire->port_id] = wire;
 			if (wire->port_output) {
 				outputs[wire->port_id] = wire;
-				if (wire->name.find("safety") != std::string::npos )
+				if (wire->name.str().find("safety") != std::string::npos )
 					safety.push_back(wire);
 			}
 		}
diff --git a/backends/edif/edif.cc b/backends/edif/edif.cc
index 49f719a4a..bf1efc4ae 100644
--- a/backends/edif/edif.cc
+++ b/backends/edif/edif.cc
@@ -108,7 +108,7 @@ struct EdifBackend : public Backend {
 		log_header("Executing EDIF backend.\n");
 
 		std::string top_module_name;
-		std::map<std::string, std::set<std::string>> lib_cell_ports;
+		std::map<RTLIL::IdString, std::set<RTLIL::IdString>> lib_cell_ports;
 		CellTypes ct(design);
 		EdifNames edif_names;
 
diff --git a/backends/verilog/verilog_backend.cc b/backends/verilog/verilog_backend.cc
index 4bba32a63..e3c930c8b 100644
--- a/backends/verilog/verilog_backend.cc
+++ b/backends/verilog/verilog_backend.cc
@@ -39,14 +39,14 @@ namespace {
 
 bool norename, noattr, attr2comment, noexpr;
 int auto_name_counter, auto_name_offset, auto_name_digits;
-std::map<std::string, int> auto_name_map;
+std::map<RTLIL::IdString, int> auto_name_map;
 
-std::set<std::string> reg_wires;
+std::set<RTLIL::IdString> reg_wires;
 
 CellTypes reg_ct;
 RTLIL::Module *active_module;
 
-void reset_auto_counter_id(const std::string &id, bool may_rename)
+void reset_auto_counter_id(RTLIL::IdString id, bool may_rename)
 {
 	const char *str = id.c_str();
 
@@ -94,7 +94,7 @@ void reset_auto_counter(RTLIL::Module *module)
 		log("  renaming `%s' to `_%0*d_'.\n", it->first.c_str(), auto_name_digits, auto_name_offset + it->second);
 }
 
-std::string id(std::string internal_id, bool may_rename = true)
+std::string id(RTLIL::IdString internal_id, bool may_rename = true)
 {
 	const char *str = internal_id.c_str();
 	bool do_escape = false;
@@ -324,7 +324,7 @@ std::string cellname(RTLIL::Cell *cell)
 		if (wire->name[0] != '\\')
 			goto no_special_reg_name;
 
-		std::string cell_name = wire->name;
+		std::string cell_name = wire->name.str();
 
 		size_t pos = cell_name.find('[');
 		if (pos != std::string::npos)
@@ -715,7 +715,7 @@ void dump_cell(FILE *f, std::string indent, RTLIL::Cell *cell)
 		fprintf(f, " %s (", cell_name.c_str());
 
 	bool first_arg = true;
-	std::set<std::string> numbered_ports;
+	std::set<RTLIL::IdString> numbered_ports;
 	for (int i = 1; true; i++) {
 		char str[16];
 		snprintf(str, 16, "$%d", i);
diff --git a/frontends/ast/genrtlil.cc b/frontends/ast/genrtlil.cc
index f4f82823b..bea99d8d4 100644
--- a/frontends/ast/genrtlil.cc
+++ b/frontends/ast/genrtlil.cc
@@ -48,7 +48,7 @@ static RTLIL::SigSpec uniop2rtlil(AstNode *that, std::string type, int result_wi
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
-	RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
+	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
 	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
 	if (gen_attributes)
@@ -82,7 +82,7 @@ static void widthExtend(AstNode *that, RTLIL::SigSpec &sig, int width, bool is_s
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), celltype);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
-	RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", width);
+	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", width);
 	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
 	if (that != NULL)
@@ -111,7 +111,7 @@ static RTLIL::SigSpec binop2rtlil(AstNode *that, std::string type, int result_wi
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), type);
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
-	RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", result_width);
+	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", result_width);
 	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
 	for (auto &attr : that->attributes) {
@@ -146,7 +146,7 @@ static RTLIL::SigSpec mux2rtlil(AstNode *that, const RTLIL::SigSpec &cond, const
 	RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$mux");
 	cell->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
-	RTLIL::Wire *wire = current_module->addWire(cell->name + "_Y", left.size());
+	RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_Y", left.size());
 	wire->attributes["\\src"] = stringf("%s:%d", that->filename.c_str(), that->linenum);
 
 	for (auto &attr : that->attributes) {
@@ -295,7 +295,7 @@ struct AST_INTERNAL::ProcessGenerator
 			do {
 				wire_name = stringf("$%d%s[%d:%d]", new_temp_count[chunk.wire]++,
 						chunk.wire->name.c_str(), chunk.width+chunk.offset-1, chunk.offset);;
-				if (chunk.wire->name.find('$') != std::string::npos)
+				if (chunk.wire->name.str().find('$') != std::string::npos)
 					wire_name += stringf("$%d", autoidx++);
 			} while (current_module->wires_.count(wire_name) > 0);
 
@@ -1196,7 +1196,7 @@ RTLIL::SigSpec AstNode::genRTLIL(int width_hint, bool sign_hint)
 			RTLIL::Cell *cell = current_module->addCell(sstr.str(), "$memrd");
 			cell->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 
-			RTLIL::Wire *wire = current_module->addWire(cell->name + "_DATA", current_module->memories[str]->width);
+			RTLIL::Wire *wire = current_module->addWire(cell->name.str() + "_DATA", current_module->memories[str]->width);
 			wire->attributes["\\src"] = stringf("%s:%d", filename.c_str(), linenum);
 
 			int addr_bits = 1;
diff --git a/kernel/rtlil.cc b/kernel/rtlil.cc
index 137058522..af652a9d6 100644
--- a/kernel/rtlil.cc
+++ b/kernel/rtlil.cc
@@ -1998,7 +1998,7 @@ void RTLIL::SigSpec::hash() const
 			for (auto &v : c.data.bits)
 				DJB2(that->hash_, v);
 		} else {
-			for (auto &v : c.wire->name)
+			for (auto &v : c.wire->name.str())
 				DJB2(that->hash_, v);
 			DJB2(that->hash_, c.offset);
 			DJB2(that->hash_, c.width);
diff --git a/kernel/rtlil.h b/kernel/rtlil.h
index b423b1bc9..70e01b721 100644
--- a/kernel/rtlil.h
+++ b/kernel/rtlil.h
@@ -72,70 +72,43 @@ namespace RTLIL
 
 	typedef std::pair<SigSpec, SigSpec> SigSig;
 
-#if 1
-	struct IdString : public std::string {
-		IdString() { }
-		IdString(std::string str) : std::string(str) {
-			check();
-		}
-		IdString(const char *s) : std::string(s) {
-			check();
-		}
-		IdString &operator=(const std::string &str) {
-			std::string::operator=(str);
-			check();
-			return *this;
-		}
-		IdString &operator=(const char *s) {
-			std::string::operator=(s);
-			check();
-			return *this;
-		}
-		bool operator<(const IdString &rhs) {
-			check(), rhs.check();
-			return std::string(*this) < std::string(rhs);
-		}
-		void check() const {
-			log_assert(empty() || (size() >= 2 && (at(0) == '$' || at(0) == '\\')));
-		}
-		const std::string& str() const {
-			return *this;
-		}
-	};
-#else
-	struct IdString {
-		IdString();
-		IdString(const char *str);
-		IdString(const IdString &str);
-		IdString(const std::string &str);
-
-		void operator=(const char *rhs);
-		void operator=(const IdString &rhs);
-		void operator=(const std::string &rhs);
-
-		operator const char*() const;
-		const std::string& str() const;
-
-		bool operator<(const IdString &rhs) const;
-		bool operator==(const IdString &rhs) const;
-		bool operator!=(const IdString &rhs) const;
-		bool operator==(const char *rhs) const;
-		bool operator!=(const char *rhs) const;
-		std::string operator+(const char *other) const;
-
-		std::string::const_iterator begin() const;
-		std::string::const_iterator end() const;
-		char at(int i) const;
-		const char*c_str() const;
-		size_t find(char c) const;
-		std::string substr(size_t pos = 0, size_t len = std::string::npos) const;
-		size_t size() const;
-		bool empty() const;
-		void clear();
+	struct IdString
+	{
+	private:
+		std::string str_;
+	
+	public:
+		IdString() : str_() { }
+		IdString(const char *str) : str_(str) { }
+		IdString(const IdString &str) : str_(str.str_) { }
+		IdString(const std::string &str) : str_(str) { }
+
+		void operator=(const char *rhs) { str_ = rhs; }
+		void operator=(const IdString &rhs) { str_ = rhs.str_; }
+		void operator=(const std::string &rhs) { str_ = rhs; }
+
+		const std::string& str() const { return str_; }
+
+		// The methods below are just convinience functions for better compatibility
+		// with std::string. Except clear() they all just deligate to std::string.
+
+		operator const char*() const { return str().c_str(); }
+
+		bool operator<(const IdString &rhs) const { return str() < rhs.str(); }
+		bool operator==(const IdString &rhs) const { return str() == rhs.str(); }
+		bool operator!=(const IdString &rhs) const { return str() != rhs.str(); }
+
+		bool operator==(const char *rhs) const { return str() == rhs; }
+		bool operator!=(const char *rhs) const { return str() != rhs; }
+
+		char at(size_t i) const { return str().at(i); }
+		const char*c_str() const { return str().c_str(); }
+		std::string substr(size_t pos = 0, size_t len = std::string::npos) const { return str().substr(pos, len); }
+		size_t size() const { return str().size(); }
+		bool empty() const { return str().empty(); }
+		void clear() { *this = IdString(); }
 	};
 
-#endif
-
 	static inline std::string escape_id(std::string str) {
 		if (str.size() > 0 && str[0] != '\\' && str[0] != '$')
 			return "\\" + str;
diff --git a/passes/cmds/connwrappers.cc b/passes/cmds/connwrappers.cc
index 5125ff5e2..aac117169 100644
--- a/passes/cmds/connwrappers.cc
+++ b/passes/cmds/connwrappers.cc
@@ -30,8 +30,8 @@ struct ConnwrappersWorker
 		bool is_signed;
 	};
 
-	std::set<std::string> decl_celltypes;
-	std::map<std::pair<std::string, std::string>, portdecl_t> decls;
+	std::set<RTLIL::IdString> decl_celltypes;
+	std::map<std::pair<RTLIL::IdString, RTLIL::IdString>, portdecl_t> decls;
 
 	void add_port(std::string celltype, std::string portname, std::string widthparam, std::string signparam)
 	{
@@ -76,7 +76,7 @@ struct ConnwrappersWorker
 
 			for (auto &conn : cell->connections())
 			{
-				std::pair<std::string, std::string> key(cell->type, conn.first);
+				std::pair<RTLIL::IdString, RTLIL::IdString> key(cell->type, conn.first);
 
 				if (!decls.count(key))
 					continue;
diff --git a/passes/cmds/show.cc b/passes/cmds/show.cc
index a2dd8051b..bbc0ff44f 100644
--- a/passes/cmds/show.cc
+++ b/passes/cmds/show.cc
@@ -111,7 +111,7 @@ struct ShowWorker
 		return stringf("style=\"setlinewidth(3)\", label=\"<%d>\"", bits);
 	}
 
-	const char *findColor(std::string member_name)
+	const char *findColor(RTLIL::IdString member_name)
 	{
 		for (auto &s : color_selections)
 			if (s.second.selected_member(module->name, member_name)) {
@@ -121,20 +121,22 @@ struct ShowWorker
 		return "";
 	}
 
-	const char *findLabel(std::string member_name)
+	const char *findLabel(RTLIL::IdString member_name)
 	{
 		for (auto &s : label_selections)
-			if (s.second.selected_member(module->name, RTLIL::escape_id(member_name)))
+			if (s.second.selected_member(module->name, member_name))
 				return escape(s.first);
 		return escape(member_name, true);
 	}
 
-	const char *escape(std::string id, bool is_name = false)
+	const char *escape(RTLIL::IdString id, bool is_name = false)
 	{
-		if (id.size() == 0)
+		std::string id_str = id.str();
+
+		if (id_str.size() == 0)
 			return "";
 
-		if (id[0] == '$' && is_name) {
+		if (id_str[0] == '$' && is_name) {
 			if (enumerateIds) {
 				if (autonames.count(id) == 0) {
 					autonames[id] = autonames.size() + 1;
@@ -142,17 +144,17 @@ struct ShowWorker
 				}
 				id = stringf("_%d_", autonames[id]);
 			} else if (abbreviateIds) {
-				const char *p = id.c_str();
+				const char *p = id_str.c_str();
 				const char *q = strrchr(p, '$');
-				id = std::string(q);
+				id_str = std::string(q);
 			}
 		}
 
-		if (id[0] == '\\')
-			id = id.substr(1);
+		if (id_str[0] == '\\')
+			id_str = id_str.substr(1);
 
 		std::string str;
-		for (char ch : id) {
+		for (char ch : id_str) {
 			if (ch == '\\' || ch == '"')
 				str += "\\";
 			str += ch;
diff --git a/passes/cmds/splice.cc b/passes/cmds/splice.cc
index 07c6150cc..ca71f7d8d 100644
--- a/passes/cmds/splice.cc
+++ b/passes/cmds/splice.cc
@@ -33,8 +33,8 @@ struct SpliceWorker
 	bool sel_by_wire;
 	bool sel_any_bit;
 	bool no_outputs;
-	std::set<std::string> ports;
-	std::set<std::string> no_ports;
+	std::set<RTLIL::IdString> ports;
+	std::set<RTLIL::IdString> no_ports;
 
 	CellTypes ct;
 	SigMap sigmap;
@@ -224,7 +224,7 @@ struct SpliceWorker
 
 		for (auto &it : rework_wires)
 		{
-			std::string orig_name = it.first->name;
+			RTLIL::IdString orig_name = it.first->name;
 			module->rename(it.first, NEW_ID);
 
 			RTLIL::Wire *new_port = module->addWire(orig_name, it.first);
@@ -283,7 +283,7 @@ struct SplicePass : public Pass {
 		bool sel_by_wire = false;
 		bool sel_any_bit = false;
 		bool no_outputs = false;
-		std::set<std::string> ports, no_ports;
+		std::set<RTLIL::IdString> ports, no_ports;
 
 		size_t argidx;
 		for (argidx = 1; argidx < args.size(); argidx++) {
diff --git a/passes/cmds/splitnets.cc b/passes/cmds/splitnets.cc
index 6b1dbe13c..a3daf2398 100644
--- a/passes/cmds/splitnets.cc
+++ b/passes/cmds/splitnets.cc
@@ -28,7 +28,7 @@ struct SplitnetsWorker
 
 	void append_wire(RTLIL::Module *module, RTLIL::Wire *wire, int offset, int width, std::string format)
 	{
-		std::string new_wire_name = wire->name;
+		std::string new_wire_name = wire->name.str();
 
 		if (format.size() > 0)
 			new_wire_name += format.substr(0, 1);
diff --git a/passes/fsm/fsm_detect.cc b/passes/fsm/fsm_detect.cc
index 6025de15b..5675dff50 100644
--- a/passes/fsm/fsm_detect.cc
+++ b/passes/fsm/fsm_detect.cc
@@ -26,7 +26,7 @@
 
 static RTLIL::Module *module;
 static SigMap assign_map;
-typedef std::pair<RTLIL::Cell*,std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::Cell*, RTLIL::IdString> sig2driver_entry_t;
 static SigSet<sig2driver_entry_t> sig2driver, sig2user;
 static std::set<RTLIL::Cell*> muxtree_cells;
 static SigPool sig_at_port;
diff --git a/passes/fsm/fsm_export.cc b/passes/fsm/fsm_export.cc
index f6f9faa9b..97ccf91ea 100644
--- a/passes/fsm/fsm_export.cc
+++ b/passes/fsm/fsm_export.cc
@@ -62,7 +62,7 @@ void write_kiss2(struct RTLIL::Module *module, struct RTLIL::Cell *cell, std::st
 	}
 	else {
 		kiss_name.assign(module->name);
-		kiss_name.append('-' + cell->name + ".kiss2");
+		kiss_name.append('-' + cell->name.str() + ".kiss2");
 	}
 
 	log("\n");
diff --git a/passes/fsm/fsm_extract.cc b/passes/fsm/fsm_extract.cc
index cf2075fba..5e71c1f0c 100644
--- a/passes/fsm/fsm_extract.cc
+++ b/passes/fsm/fsm_extract.cc
@@ -31,7 +31,7 @@
 
 static RTLIL::Module *module;
 static SigMap assign_map;
-typedef std::pair<std::string, std::string> sig2driver_entry_t;
+typedef std::pair<RTLIL::IdString, RTLIL::IdString> sig2driver_entry_t;
 static SigSet<sig2driver_entry_t> sig2driver, sig2trigger;
 
 static bool find_states(RTLIL::SigSpec sig, const RTLIL::SigSpec &dff_out, RTLIL::SigSpec &ctrl, std::map<RTLIL::Const, int> &states, RTLIL::Const *reset_state = NULL)
@@ -277,7 +277,7 @@ static void extract_fsm(RTLIL::Wire *wire)
 	fsm_cell->parameters["\\ARST_POLARITY"] = RTLIL::Const(arst_polarity ? 1 : 0, 1);
 	fsm_cell->setPort("\\CTRL_IN", ctrl_in);
 	fsm_cell->setPort("\\CTRL_OUT", ctrl_out);
-	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name);
+	fsm_cell->parameters["\\NAME"] = RTLIL::Const(wire->name.str());
 	fsm_cell->attributes = wire->attributes;
 	fsm_data.copy_to_cell(fsm_cell);
 
diff --git a/passes/hierarchy/hierarchy.cc b/passes/hierarchy/hierarchy.cc
index 67b57a94d..28b4ad990 100644
--- a/passes/hierarchy/hierarchy.cc
+++ b/passes/hierarchy/hierarchy.cc
@@ -35,7 +35,7 @@ namespace {
 
 static void generate(RTLIL::Design *design, const std::vector<std::string> &celltypes, const std::vector<generate_port_decl_t> &portdecls)
 {
-	std::set<std::string> found_celltypes;
+	std::set<RTLIL::IdString> found_celltypes;
 
 	for (auto i1 : design->modules_)
 	for (auto i2 : i1.second->cells_)
@@ -52,9 +52,9 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 
 	for (auto &celltype : found_celltypes)
 	{
-		std::set<std::string> portnames;
-		std::set<std::string> parameters;
-		std::map<std::string, int> portwidths;
+		std::set<RTLIL::IdString> portnames;
+		std::set<RTLIL::IdString> parameters;
+		std::map<RTLIL::IdString, int> portwidths;
 		log("Generate module for cell type %s:\n", celltype.c_str());
 
 		for (auto i1 : design->modules_)
@@ -94,7 +94,7 @@ static void generate(RTLIL::Design *design, const std::vector<std::string> &cell
 			}
 
 		while (portnames.size() > 0) {
-			std::string portname = *portnames.begin();
+			RTLIL::IdString portname = *portnames.begin();
 			for (auto &decl : portdecls)
 				if (decl.index == 0 && !fnmatch(decl.portname.c_str(), RTLIL::unescape_id(portname).c_str(), FNM_NOESCAPE)) {
 					generate_port_decl_t d = decl;
@@ -144,20 +144,20 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 		RTLIL::Cell *cell = cell_it.second;
 
 		if (cell->type.substr(0, 7) == "$array:") {
-			int pos_idx = cell->type.find_first_of(':');
-			int pos_num = cell->type.find_first_of(':', pos_idx + 1);
-			int pos_type = cell->type.find_first_of(':', pos_num + 1);
-			int idx = atoi(cell->type.substr(pos_idx + 1, pos_num).c_str());
-			int num = atoi(cell->type.substr(pos_num + 1, pos_type).c_str());
+			int pos_idx = cell->type.str().find_first_of(':');
+			int pos_num = cell->type.str().find_first_of(':', pos_idx + 1);
+			int pos_type = cell->type.str().find_first_of(':', pos_num + 1);
+			int idx = atoi(cell->type.str().substr(pos_idx + 1, pos_num).c_str());
+			int num = atoi(cell->type.str().substr(pos_num + 1, pos_type).c_str());
 			array_cells[cell] = std::pair<int, int>(idx, num);
-			cell->type = cell->type.substr(pos_type + 1);
+			cell->type = cell->type.str().substr(pos_type + 1);
 		}
 
 		if (design->modules_.count(cell->type) == 0)
 		{
-			if (design->modules_.count("$abstract" + cell->type))
+			if (design->modules_.count("$abstract" + cell->type.str()))
 			{
-				cell->type = design->modules_.at("$abstract" + cell->type)->derive(design, cell->parameters);
+				cell->type = design->modules_.at("$abstract" + cell->type.str())->derive(design, cell->parameters);
 				cell->parameters.clear();
 				did_something = true;
 				continue;
@@ -220,7 +220,7 @@ static bool expand_module(RTLIL::Design *design, RTLIL::Module *module, bool fla
 
 		for (auto &conn : cell->connections_) {
 			int conn_size = conn.second.size();
-			std::string portname = conn.first;
+			RTLIL::IdString portname = conn.first;
 			if (portname.substr(0, 1) == "$") {
 				int port_id = atoi(portname.substr(1).c_str());
 				for (auto &wire_it : mod->wires_)
@@ -447,7 +447,7 @@ struct HierarchyPass : public Pass {
 		bool did_something_once = false;
 		while (did_something) {
 			did_something = false;
-			std::vector<std::string> modnames;
+			std::vector<RTLIL::IdString> modnames;
 			modnames.reserve(design->modules_.size());
 			for (auto &mod_it : design->modules_)
 				modnames.push_back(mod_it.first);
diff --git a/passes/hierarchy/submod.cc b/passes/hierarchy/submod.cc
index 2a47002ef..89f45e025 100644
--- a/passes/hierarchy/submod.cc
+++ b/passes/hierarchy/submod.cc
@@ -108,7 +108,7 @@ struct SubmodWorker
 		design->add(new_mod);
 		int port_counter = 1, auto_name_counter = 1;
 
-		std::set<std::string> all_wire_names;
+		std::set<RTLIL::IdString> all_wire_names;
 		for (auto &it : wire_flags) {
 			all_wire_names.insert(it.first->name);
 		}
@@ -134,7 +134,7 @@ struct SubmodWorker
 			if (flags.is_int_driven && flags.is_ext_driven)
 				new_wire_port_input = true, new_wire_port_output = true;
 
-			std::string new_wire_name = wire->name;
+			std::string new_wire_name = wire->name.str();
 			if (new_wire_port_input || new_wire_port_output) {
 				while (new_wire_name[0] == '$') {
 					std::string next_wire_name = stringf("\\n%d", auto_name_counter++);
@@ -228,7 +228,7 @@ struct SubmodWorker
 
 				if (submodules.count(submod_str) == 0) {
 					submodules[submod_str].name = submod_str;
-					submodules[submod_str].full_name = module->name + "_" + submod_str;
+					submodules[submod_str].full_name = module->name.str() + "_" + submod_str;
 					while (design->modules_.count(submodules[submod_str].full_name) != 0 ||
 							module->count_id(submodules[submod_str].full_name) != 0)
 						submodules[submod_str].full_name += "_";
@@ -306,12 +306,12 @@ struct SubmodPass : public Pass {
 			Pass::call(design, "opt_clean");
 			log_header("Continuing SUBMOD pass.\n");
 
-			std::set<std::string> handled_modules;
+			std::set<RTLIL::IdString> handled_modules;
 
 			bool did_something = true;
 			while (did_something) {
 				did_something = false;
-				std::vector<std::string> queued_modules;
+				std::vector<RTLIL::IdString> queued_modules;
 				for (auto &mod_it : design->modules_)
 					if (handled_modules.count(mod_it.first) == 0 && design->selected_whole_module(mod_it.first))
 						queued_modules.push_back(mod_it.first);
diff --git a/passes/memory/memory_collect.cc b/passes/memory/memory_collect.cc
index 8887d1952..471a7d53a 100644
--- a/passes/memory/memory_collect.cc
+++ b/passes/memory/memory_collect.cc
@@ -62,7 +62,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 
 	for (auto &cell_it : module->cells_) {
 		RTLIL::Cell *cell = cell_it.second;
-		if ((cell->type == "$memwr" || cell->type == "$memrd") && cell->parameters["\\MEMID"].decode_string() == memory->name)
+		if ((cell->type == "$memwr" || cell->type == "$memrd") && memory->name == cell->parameters["\\MEMID"].decode_string())
 			memcells.push_back(cell);
 	}
 
@@ -70,7 +70,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 
 	for (auto cell : memcells)
 	{
-		if (cell->type == "$memwr" && cell->parameters["\\MEMID"].decode_string() == memory->name)
+		if (cell->type == "$memwr" && memory->name == cell->parameters["\\MEMID"].decode_string())
 		{
 			wr_ports++;
 			del_cells.push_back(cell);
@@ -97,7 +97,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 			sig_wr_en.append(en);
 		}
 
-		if (cell->type == "$memrd" && cell->parameters["\\MEMID"].decode_string() == memory->name)
+		if (cell->type == "$memrd" && memory->name == cell->parameters["\\MEMID"].decode_string())
 		{
 			rd_ports++;
 			del_cells.push_back(cell);
@@ -129,7 +129,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Memory *memory)
 	sstr << "$mem$" << memory->name << "$" << (autoidx++);
 
 	RTLIL::Cell *mem = module->addCell(sstr.str(), "$mem");
-	mem->parameters["\\MEMID"] = RTLIL::Const(memory->name);
+	mem->parameters["\\MEMID"] = RTLIL::Const(memory->name.str());
 	mem->parameters["\\WIDTH"] = RTLIL::Const(memory->width);
 	mem->parameters["\\OFFSET"] = RTLIL::Const(memory->start_offset);
 	mem->parameters["\\SIZE"] = RTLIL::Const(memory->size);
diff --git a/passes/memory/memory_map.cc b/passes/memory/memory_map.cc
index f1917b972..8dc66f2cd 100644
--- a/passes/memory/memory_map.cc
+++ b/passes/memory/memory_map.cc
@@ -23,10 +23,10 @@
 #include <set>
 #include <stdlib.h>
 
-static std::string genid(std::string name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
+static std::string genid(RTLIL::IdString name, std::string token1 = "", int i = -1, std::string token2 = "", int j = -1, std::string token3 = "", int k = -1, std::string token4 = "")
 {
 	std::stringstream sstr;
-	sstr << "$memory" << name << token1;
+	sstr << "$memory" << name.str() << token1;
 	
 	if (i >= 0)
 		sstr << "[" << i << "]";
diff --git a/passes/memory/memory_unpack.cc b/passes/memory/memory_unpack.cc
index 68e9a9697..5a4c4eac9 100644
--- a/passes/memory/memory_unpack.cc
+++ b/passes/memory/memory_unpack.cc
@@ -31,7 +31,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	RTLIL::IdString mem_name = RTLIL::escape_id(memory->parameters.at("\\MEMID").decode_string());
 
 	while (module->memories.count(mem_name) != 0)
-		mem_name += stringf("_%d", autoidx++);
+		mem_name = mem_name.str() + stringf("_%d", autoidx++);
 
 	RTLIL::Memory *mem = new RTLIL::Memory;
 	mem->name = mem_name;
@@ -47,7 +47,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	for (int i = 0; i < num_rd_ports; i++)
 	{
 		RTLIL::Cell *cell = module->addCell(NEW_ID, "$memrd");
-		cell->parameters["\\MEMID"] = mem_name;
+		cell->parameters["\\MEMID"] = mem_name.str();
 		cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
 		cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\RD_CLK_ENABLE")).extract(i, 1).as_const();
@@ -61,7 +61,7 @@ static void handle_memory(RTLIL::Module *module, RTLIL::Cell *memory)
 	for (int i = 0; i < num_wr_ports; i++)
 	{
 		RTLIL::Cell *cell = module->addCell(NEW_ID, "$memwr");
-		cell->parameters["\\MEMID"] = mem_name;
+		cell->parameters["\\MEMID"] = mem_name.str();
 		cell->parameters["\\ABITS"] = memory->parameters.at("\\ABITS");
 		cell->parameters["\\WIDTH"] = memory->parameters.at("\\WIDTH");
 		cell->parameters["\\CLK_ENABLE"] = RTLIL::SigSpec(memory->parameters.at("\\WR_CLK_ENABLE")).extract(i, 1).as_const();
diff --git a/passes/opt/opt_clean.cc b/passes/opt/opt_clean.cc
index 4182c6f5d..c620531e3 100644
--- a/passes/opt/opt_clean.cc
+++ b/passes/opt/opt_clean.cc
@@ -139,11 +139,12 @@ static bool compare_signals(RTLIL::SigBit &s1, RTLIL::SigBit &s2, SigPool &regs,
 
 static bool check_public_name(RTLIL::IdString id)
 {
-	if (id[0] == '$')
+	const std::string &id_str = id.str();
+	if (id_str[0] == '$')
 		return false;
-	if (id.substr(0, 2) == "\\_" && (id[id.size()-1] == '_' || id.find("_[") != std::string::npos))
+	if (id_str.substr(0, 2) == "\\_" && (id_str[id_str.size()-1] == '_' || id_str.find("_[") != std::string::npos))
 		return false;
-	if (id.find(".$") != std::string::npos)
+	if (id_str.find(".$") != std::string::npos)
 		return false;
 	return true;
 }
diff --git a/passes/opt/opt_const.cc b/passes/opt/opt_const.cc
index 5dab5ecab..a13bb09cb 100644
--- a/passes/opt/opt_const.cc
+++ b/passes/opt/opt_const.cc
@@ -183,7 +183,7 @@ static bool group_cell_inputs(RTLIL::Module *module, RTLIL::Cell *cell, bool com
 		log("\n");
 	}
 
-	cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type);
+	cover_list("opt.opt_const.fine.group", "$not", "$pos", "$bu0", "$and", "$or", "$xor", "$xnor", cell->type.str());
 
 	module->remove(cell);
 	OPT_DID_SOMETHING = true;
@@ -288,7 +288,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					}
 
 				if (new_a != RTLIL::State::Sm && RTLIL::SigSpec(new_a) != sig_a) {
-					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type);
+					cover_list("opt.opt_const.fine.A", "$logic_not", "$logic_and", "$logic_or", "$reduce_or", "$reduce_bool", cell->type.str());
 					log("Replacing port A of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_a), log_signal(new_a));
 					cell->setPort("\\A", sig_a = new_a);
@@ -315,7 +315,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					}
 
 				if (new_b != RTLIL::State::Sm && RTLIL::SigSpec(new_b) != sig_b) {
-					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type);
+					cover_list("opt.opt_const.fine.B", "$logic_and", "$logic_or", cell->type.str());
 					log("Replacing port B of %s cell `%s' in module `%s' with constant driver: %s -> %s\n",
 							cell->type.c_str(), cell->name.c_str(), module->name.c_str(), log_signal(sig_b), log_signal(new_b));
 					cell->setPort("\\B", sig_b = new_b);
@@ -361,7 +361,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			if (0) {
 		found_the_x_bit:
 				cover_list("opt.opt_const.xbit", "$reduce_xor", "$reduce_xnor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx",
-						"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type);
+						"$lt", "$le", "$ge", "$gt", "$neg", "$add", "$sub", "$mul", "$div", "$mod", "$pow", cell->type.str());
 				if (cell->type == "$reduce_xor" || cell->type == "$reduce_xnor" ||
 						cell->type == "$lt" || cell->type == "$le" || cell->type == "$ge" || cell->type == "$gt")
 					replace_cell(assign_map, module, cell, "x-bit in input", "\\Y", RTLIL::State::Sx);
@@ -373,13 +373,13 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if ((cell->type == "$_INV_" || cell->type == "$not" || cell->type == "$logic_not") && cell->getPort("\\Y").size() == 1 &&
 				invert_map.count(assign_map(cell->getPort("\\A"))) != 0) {
-			cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type);
+			cover_list("opt.opt_const.invert.double", "$_INV_", "$not", "$logic_not", cell->type.str());
 			replace_cell(assign_map, module, cell, "double_invert", "\\Y", invert_map.at(assign_map(cell->getPort("\\A"))));
 			goto next_cell;
 		}
 
 		if ((cell->type == "$_MUX_" || cell->type == "$mux") && invert_map.count(assign_map(cell->getPort("\\S"))) != 0) {
-			cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type);
+			cover_list("opt.opt_const.invert.muxsel", "$_MUX_", "$mux", cell->type.str());
 			RTLIL::SigSpec tmp = cell->getPort("\\A");
 			cell->setPort("\\A", cell->getPort("\\B"));
 			cell->setPort("\\B", tmp);
@@ -497,7 +497,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			log_assert(SIZE(a) == SIZE(b));
 			for (int i = 0; i < SIZE(a); i++) {
 				if (a[i].wire == NULL && b[i].wire == NULL && a[i] != b[i] && a[i].data <= RTLIL::State::S1 && b[i].data <= RTLIL::State::S1) {
-					cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type);
+					cover_list("opt.opt_const.eqneq.isneq", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
 					RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S0 : RTLIL::State::S1);
 					new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 					replace_cell(assign_map, module, cell, "isneq", "\\Y", new_y);
@@ -510,7 +510,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 
 			if (new_a.size() == 0) {
-				cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type);
+				cover_list("opt.opt_const.eqneq.empty", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
 				RTLIL::SigSpec new_y = RTLIL::SigSpec((cell->type == "$eq" || cell->type == "$eqx") ?  RTLIL::State::S1 : RTLIL::State::S0);
 				new_y.extend(cell->parameters["\\Y_WIDTH"].as_int(), false);
 				replace_cell(assign_map, module, cell, "empty", "\\Y", new_y);
@@ -518,7 +518,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			}
 
 			if (new_a.size() < a.size() || new_b.size() < b.size()) {
-				cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type);
+				cover_list("opt.opt_const.eqneq.resize", "$eq", "$ne", "$eqx", "$nex", cell->type.str());
 				cell->setPort("\\A", new_a);
 				cell->setPort("\\B", new_b);
 				cell->parameters["\\A_WIDTH"] = new_a.size();
@@ -533,7 +533,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			RTLIL::SigSpec b = assign_map(cell->getPort("\\B"));
 
 			if (a.is_fully_const()) {
-				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type);
+				cover_list("opt.opt_const.eqneq.swapconst", "$eq", "$ne", cell->type.str());
 				RTLIL::SigSpec tmp = cell->getPort("\\A");
 				cell->setPort("\\A", cell->getPort("\\B"));
 				cell->setPort("\\B", tmp);
@@ -544,7 +544,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 					RTLIL::SigSpec input = b;
 					ACTION_DO("\\Y", cell->getPort("\\A"));
 				} else {
-					cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type);
+					cover_list("opt.opt_const.eqneq.isnot", "$eq", "$ne", cell->type.str());
 					cell->type = "$not";
 					cell->parameters.erase("\\B_WIDTH");
 					cell->parameters.erase("\\B_SIGNED");
@@ -603,9 +603,9 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			if (identity_wrt_a || identity_wrt_b)
 			{
 				if (identity_wrt_a)
-					cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type);
+					cover_list("opt.opt_const.identwrt.a", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
 				if (identity_wrt_b)
-					cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type);
+					cover_list("opt.opt_const.identwrt.b", "$add", "$sub", "$or", "$xor", "$shl", "$shr", "$sshl", "$sshr", "$shift", "$shiftx", "$mul", "$div", cell->type.str());
 
 				log("Replacing %s cell `%s' in module `%s' with identity for port %c.\n",
 					cell->type.c_str(), cell->name.c_str(), module->name.c_str(), identity_wrt_a ? 'A' : 'B');
@@ -630,14 +630,14 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
 				cell->getPort("\\A") == RTLIL::SigSpec(0, 1) && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
-			cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type);
+			cover_list("opt.opt_const.mux_bool", "$mux", "$_MUX_", cell->type.str());
 			replace_cell(assign_map, module, cell, "mux_bool", "\\Y", cell->getPort("\\S"));
 			goto next_cell;
 		}
 
 		if (mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") &&
 				cell->getPort("\\A") == RTLIL::SigSpec(1, 1) && cell->getPort("\\B") == RTLIL::SigSpec(0, 1)) {
-			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type);
+			cover_list("opt.opt_const.mux_invert", "$mux", "$_MUX_", cell->type.str());
 			cell->setPort("\\A", cell->getPort("\\S"));
 			cell->unsetPort("\\B");
 			cell->unsetPort("\\S");
@@ -655,7 +655,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\A") == RTLIL::SigSpec(0, 1)) {
-			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type);
+			cover_list("opt.opt_const.mux_and", "$mux", "$_MUX_", cell->type.str());
 			cell->setPort("\\A", cell->getPort("\\S"));
 			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
@@ -674,7 +674,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 		}
 
 		if (consume_x && mux_bool && (cell->type == "$mux" || cell->type == "$_MUX_") && cell->getPort("\\B") == RTLIL::SigSpec(1, 1)) {
-			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type);
+			cover_list("opt.opt_const.mux_or", "$mux", "$_MUX_", cell->type.str());
 			cell->setPort("\\B", cell->getPort("\\S"));
 			cell->unsetPort("\\S");
 			if (cell->type == "$mux") {
@@ -697,7 +697,7 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 			int width = cell->getPort("\\A").size();
 			if ((cell->getPort("\\A").is_fully_undef() && cell->getPort("\\B").is_fully_undef()) ||
 					cell->getPort("\\S").is_fully_undef()) {
-				cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type);
+				cover_list("opt.opt_const.mux_undef", "$mux", "$pmux", cell->type.str());
 				replace_cell(assign_map, module, cell, "mux_undef", "\\Y", cell->getPort("\\A"));
 				goto next_cell;
 			}
@@ -716,17 +716,17 @@ static void replace_const_cells(RTLIL::Design *design, RTLIL::Module *module, bo
 				new_s = new_s.extract(0, new_s.size()-1);
 			}
 			if (new_s.size() == 0) {
-				cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type);
+				cover_list("opt.opt_const.mux_empty", "$mux", "$pmux", cell->type.str());
 				replace_cell(assign_map, module, cell, "mux_empty", "\\Y", new_a);
 				goto next_cell;
 			}
 			if (new_a == RTLIL::SigSpec(RTLIL::State::S0) && new_b == RTLIL::SigSpec(RTLIL::State::S1)) {
-				cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type);
+				cover_list("opt.opt_const.mux_sel01", "$mux", "$pmux", cell->type.str());
 				replace_cell(assign_map, module, cell, "mux_sel01", "\\Y", new_s);
 				goto next_cell;
 			}
 			if (cell->getPort("\\S").size() != new_s.size()) {
-				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type);
+				cover_list("opt.opt_const.mux_reduce", "$mux", "$pmux", cell->type.str());
 				cell->setPort("\\A", new_a);
 				cell->setPort("\\B", new_b);
 				cell->setPort("\\S", new_s);
diff --git a/passes/opt/opt_rmdff.cc b/passes/opt/opt_rmdff.cc
index c1e33caf3..bbf94d3b4 100644
--- a/passes/opt/opt_rmdff.cc
+++ b/passes/opt/opt_rmdff.cc
@@ -178,7 +178,7 @@ struct OptRmdffPass : public Pass {
 					dff_init_map.add(it.second, it.second->attributes.at("\\init"));
 			mux_drivers.clear();
 
-			std::vector<std::string> dff_list;
+			std::vector<RTLIL::IdString> dff_list;
 			for (auto &it : mod_it.second->cells_) {
 				if (it.second->type == "$mux" || it.second->type == "$pmux") {
 					if (it.second->getPort("\\A").size() == it.second->getPort("\\B").size())
diff --git a/passes/opt/opt_share.cc b/passes/opt/opt_share.cc
index 3532b124e..eb970329d 100644
--- a/passes/opt/opt_share.cc
+++ b/passes/opt/opt_share.cc
@@ -60,10 +60,10 @@ struct OptShareWorker
 		if (cell_hash_cache.count(cell) > 0)
 			return cell_hash_cache[cell];
 
-		std::string hash_string = cell->type + "\n";
+		std::string hash_string = cell->type.str() + "\n";
 
 		for (auto &it : cell->parameters)
-			hash_string += "P " + it.first + "=" + it.second.as_string() + "\n";
+			hash_string += "P " + it.first.str() + "=" + it.second.as_string() + "\n";
 
 		const std::map<RTLIL::IdString, RTLIL::SigSpec> *conn = &cell->connections();
 		std::map<RTLIL::IdString, RTLIL::SigSpec> alt_conn;
@@ -95,10 +95,10 @@ struct OptShareWorker
 				continue;
 			RTLIL::SigSpec sig = it.second;
 			assign_map.apply(sig);
-			hash_string += "C " + it.first + "=";
+			hash_string += "C " + it.first.str() + "=";
 			for (auto &chunk : sig.chunks()) {
 				if (chunk.wire)
-					hash_string += "{" + chunk.wire->name + " " +
+					hash_string += "{" + chunk.wire->name.str() + " " +
 							int_to_hash_string(chunk.offset) + " " +
 							int_to_hash_string(chunk.width) + "}";
 				else
diff --git a/passes/proc/proc_clean.cc b/passes/proc/proc_clean.cc
index e4c526632..13be0ddb6 100644
--- a/passes/proc/proc_clean.cc
+++ b/passes/proc/proc_clean.cc
@@ -150,7 +150,7 @@ struct ProcCleanPass : public Pass {
 		extra_args(args, 1, design);
 
 		for (auto mod : design->modules()) {
-			std::vector<std::string> delme;
+			std::vector<RTLIL::IdString> delme;
 			if (!design->selected(mod))
 				continue;
 			for (auto &proc_it : mod->processes) {
diff --git a/passes/sat/eval.cc b/passes/sat/eval.cc
index 8a2dd929b..f07ad943c 100644
--- a/passes/sat/eval.cc
+++ b/passes/sat/eval.cc
@@ -471,7 +471,7 @@ struct EvalPass : public Pass {
 		if (shows.size() == 0) {
 			for (auto &it : module->wires_)
 				if (it.second->port_output)
-					shows.push_back(it.second->name);
+					shows.push_back(it.second->name.str());
 		}
 
 		if (tables.empty())
diff --git a/passes/sat/expose.cc b/passes/sat/expose.cc
index 25b9e1d11..affd685e4 100644
--- a/passes/sat/expose.cc
+++ b/passes/sat/expose.cc
@@ -27,7 +27,7 @@ struct dff_map_info_t {
 	RTLIL::SigSpec sig_d, sig_clk, sig_arst;
 	bool clk_polarity, arst_polarity;
 	RTLIL::Const arst_value;
-	std::vector<std::string> cells;
+	std::vector<RTLIL::IdString> cells;
 };
 
 struct dff_map_bit_info_t {
@@ -37,7 +37,7 @@ struct dff_map_bit_info_t {
 	RTLIL::Cell *cell;
 };
 
-static bool consider_wire(RTLIL::Wire *wire, std::map<std::string, dff_map_info_t> &dff_dq_map)
+static bool consider_wire(RTLIL::Wire *wire, std::map<RTLIL::IdString, dff_map_info_t> &dff_dq_map)
 {
 	if (wire->name[0] == '$' || dff_dq_map.count(wire->name))
 		return false;
@@ -46,7 +46,7 @@ static bool consider_wire(RTLIL::Wire *wire, std::map<std::string, dff_map_info_
 	return true;
 }
 
-static bool consider_cell(RTLIL::Design *design, std::set<std::string> &dff_cells, RTLIL::Cell *cell)
+static bool consider_cell(RTLIL::Design *design, std::set<RTLIL::IdString> &dff_cells, RTLIL::Cell *cell)
 {
 	if (cell->name[0] == '$' || dff_cells.count(cell->name))
 		return false;
@@ -73,7 +73,7 @@ static bool compare_cells(RTLIL::Cell *cell1, RTLIL::Cell *cell2)
 	return true;
 }
 
-static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *module)
+static void find_dff_wires(std::set<RTLIL::IdString> &dff_wires, RTLIL::Module *module)
 {
 	CellTypes ct;
 	ct.setup_internals_mem();
@@ -93,7 +93,7 @@ static void find_dff_wires(std::set<std::string> &dff_wires, RTLIL::Module *modu
 	}
 }
 
-static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
+static void create_dff_dq_map(std::map<RTLIL::IdString, dff_map_info_t> &map, RTLIL::Design *design, RTLIL::Module *module)
 {
 	std::map<RTLIL::SigBit, dff_map_bit_info_t> bit_info;
 	SigMap sigmap(module);
@@ -160,7 +160,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 		}
 	}
 
-	std::map<std::string, dff_map_info_t> empty_dq_map;
+	std::map<RTLIL::IdString, dff_map_info_t> empty_dq_map;
 	for (auto &it : module->wires_)
 	{
 		if (!consider_wire(it.second, empty_dq_map))
@@ -208,7 +208,7 @@ static void create_dff_dq_map(std::map<std::string, dff_map_info_t> &map, RTLIL:
 	}
 }
 
-static RTLIL::Wire *add_new_wire(RTLIL::Module *module, std::string name, int width = 1)
+static RTLIL::Wire *add_new_wire(RTLIL::Module *module, RTLIL::IdString name, int width = 1)
 {
 	if (module->count_id(name))
 		log_error("Attempting to create wire %s, but a wire of this name exists already! Hint: Try another value for -sep.\n", log_id(name));
@@ -294,13 +294,13 @@ struct ExposePass : public Pass {
 
 		CellTypes ct(design);
 
-		std::map<RTLIL::Module*, std::map<std::string, dff_map_info_t>> dff_dq_maps;
-		std::map<RTLIL::Module*, std::set<std::string>> dff_cells;
+		std::map<RTLIL::Module*, std::map<RTLIL::IdString, dff_map_info_t>> dff_dq_maps;
+		std::map<RTLIL::Module*, std::set<RTLIL::IdString>> dff_cells;
 
 		if (flag_evert_dff)
 		{
 			RTLIL::Module *first_module = NULL;
-			std::set<std::string> shared_dff_wires;
+			std::set<RTLIL::IdString> shared_dff_wires;
 
 			for (auto &mod_it : design->modules_)
 			{
@@ -317,7 +317,7 @@ struct ExposePass : public Pass {
 						shared_dff_wires.insert(it.first);
 					first_module = mod_it.second;
 				} else {
-					std::set<std::string> new_shared_dff_wires;
+					std::set<RTLIL::IdString> new_shared_dff_wires;
 					for (auto &it : shared_dff_wires) {
 						if (!dff_dq_maps[mod_it.second].count(it))
 							continue;
@@ -332,7 +332,7 @@ struct ExposePass : public Pass {
 			if (flag_shared)
 				for (auto &map_it : dff_dq_maps)
 				{
-					std::map<std::string, dff_map_info_t> new_map;
+					std::map<RTLIL::IdString, dff_map_info_t> new_map;
 					for (auto &it : map_it.second)
 						if (shared_dff_wires.count(it.first))
 							new_map[it.first] = it.second;
@@ -345,8 +345,8 @@ struct ExposePass : public Pass {
 				dff_cells[it1.first].insert(it3);
 		}
 
-		std::set<std::string> shared_wires, shared_cells;
-		std::set<std::string> used_names;
+		std::set<RTLIL::IdString> shared_wires, shared_cells;
+		std::set<RTLIL::IdString> used_names;
 
 		if (flag_shared)
 		{
@@ -359,7 +359,7 @@ struct ExposePass : public Pass {
 				if (!design->selected(module))
 					continue;
 
-				std::set<std::string> dff_wires;
+				std::set<RTLIL::IdString> dff_wires;
 				if (flag_dff)
 					find_dff_wires(dff_wires, module);
 
@@ -379,7 +379,7 @@ struct ExposePass : public Pass {
 				}
 				else
 				{
-					std::vector<std::string> delete_shared_wires, delete_shared_cells;
+					std::vector<RTLIL::IdString> delete_shared_wires, delete_shared_cells;
 
 					for (auto &it : shared_wires)
 					{
@@ -441,7 +441,7 @@ struct ExposePass : public Pass {
 			if (!design->selected(module))
 				continue;
 
-			std::set<std::string> dff_wires;
+			std::set<RTLIL::IdString> dff_wires;
 			if (flag_dff && !flag_shared)
 				find_dff_wires(dff_wires, module);
 
@@ -467,7 +467,7 @@ struct ExposePass : public Pass {
 				}
 
 				if (flag_cut) {
-					RTLIL::Wire *in_wire = add_new_wire(module, it.second->name + sep + "i", it.second->width);
+					RTLIL::Wire *in_wire = add_new_wire(module, it.second->name.str() + sep + "i", it.second->width);
 					in_wire->port_input = true;
 					out_to_in_map.add(sigmap(it.second), in_wire);
 				}
@@ -511,7 +511,7 @@ struct ExposePass : public Pass {
 					cell->setPort("\\Q", cell_q_bits);
 				}
 
-				RTLIL::Wire *wire_q = add_new_wire(module, wire->name + sep + "q", wire->width);
+				RTLIL::Wire *wire_q = add_new_wire(module, wire->name.str() + sep + "q", wire->width);
 				wire_q->port_input = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_q->name));
 
@@ -525,12 +525,12 @@ struct ExposePass : public Pass {
 				}
 				module->connect(connect_q);
 
-				RTLIL::Wire *wire_d = add_new_wire(module, wire->name + sep + "d", wire->width);
+				RTLIL::Wire *wire_d = add_new_wire(module, wire->name.str() + sep + "d", wire->width);
 				wire_d->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_d->name));
 				module->connect(RTLIL::SigSig(wire_d, info.sig_d));
 
-				RTLIL::Wire *wire_c = add_new_wire(module, wire->name + sep + "c");
+				RTLIL::Wire *wire_c = add_new_wire(module, wire->name.str() + sep + "c");
 				wire_c->port_output = true;
 				log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_c->name));
 				if (info.clk_polarity) {
@@ -546,7 +546,7 @@ struct ExposePass : public Pass {
 
 				if (info.sig_arst != RTLIL::State::Sm)
 				{
-					RTLIL::Wire *wire_r = add_new_wire(module, wire->name + sep + "r");
+					RTLIL::Wire *wire_r = add_new_wire(module, wire->name.str() + sep + "r");
 					wire_r->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_r->name));
 					if (info.arst_polarity) {
@@ -560,7 +560,7 @@ struct ExposePass : public Pass {
 						c->setPort("\\Y", wire_r);
 					}
 
-					RTLIL::Wire *wire_v = add_new_wire(module, wire->name + sep + "v", wire->width);
+					RTLIL::Wire *wire_v = add_new_wire(module, wire->name.str() + sep + "v", wire->width);
 					wire_v->port_output = true;
 					log("New module port: %s/%s\n", RTLIL::id2cstr(module->name), RTLIL::id2cstr(wire_v->name));
 					module->connect(RTLIL::SigSig(wire_v, info.arst_value));
@@ -593,7 +593,7 @@ struct ExposePass : public Pass {
 							if (!p->port_input && !p->port_output)
 								continue;
 
-							RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(p->name), p->width);
+							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(p->name), p->width);
 							if (p->port_input)
 								w->port_output = true;
 							if (p->port_output)
@@ -615,7 +615,7 @@ struct ExposePass : public Pass {
 					{
 						for (auto &it : cell->connections())
 						{
-							RTLIL::Wire *w = add_new_wire(module, cell->name + sep + RTLIL::unescape_id(it.first), it.second.size());
+							RTLIL::Wire *w = add_new_wire(module, cell->name.str() + sep + RTLIL::unescape_id(it.first), it.second.size());
 							if (ct.cell_input(cell->type, it.first))
 								w->port_output = true;
 							if (ct.cell_output(cell->type, it.first))
diff --git a/passes/sat/sat.cc b/passes/sat/sat.cc
index 430628e46..fd3d405a7 100644
--- a/passes/sat/sat.cc
+++ b/passes/sat/sat.cc
@@ -1160,19 +1160,19 @@ struct SatPass : public Pass {
 		if (set_def_inputs) {
 			for (auto &it : module->wires_)
 				if (it.second->port_input)
-					sets_def.push_back(it.second->name);
+					sets_def.push_back(it.second->name.str());
 		}
 
 		if (show_inputs) {
 			for (auto &it : module->wires_)
 				if (it.second->port_input)
-					shows.push_back(it.second->name);
+					shows.push_back(it.second->name.str());
 		}
 
 		if (show_outputs) {
 			for (auto &it : module->wires_)
 				if (it.second->port_output)
-					shows.push_back(it.second->name);
+					shows.push_back(it.second->name.str());
 		}
 
 		if (tempinduct)
diff --git a/passes/sat/share.cc b/passes/sat/share.cc
index ea7a9f631..4484d6771 100644
--- a/passes/sat/share.cc
+++ b/passes/sat/share.cc
@@ -29,13 +29,13 @@ struct ShareWorkerConfig
 	bool opt_force;
 	bool opt_aggressive;
 	bool opt_fast;
-	std::set<std::string> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
+	std::set<RTLIL::IdString> generic_uni_ops, generic_bin_ops, generic_cbin_ops;
 };
 
 struct ShareWorker
 {
 	ShareWorkerConfig config;
-	std::set<std::string> generic_ops;
+	std::set<RTLIL::IdString> generic_ops;
 
 	RTLIL::Design *design;
 	RTLIL::Module *module;
diff --git a/passes/techmap/dfflibmap.cc b/passes/techmap/dfflibmap.cc
index 7712d18b9..16518b7df 100644
--- a/passes/techmap/dfflibmap.cc
+++ b/passes/techmap/dfflibmap.cc
@@ -29,7 +29,7 @@ struct cell_mapping {
 	std::string cell_name;
 	std::map<std::string, char> ports;
 };
-static std::map<std::string, cell_mapping> cell_mappings;
+static std::map<RTLIL::IdString, cell_mapping> cell_mappings;
 
 static void logmap(std::string dff)
 {
@@ -319,7 +319,7 @@ static bool expand_cellmap(std::string pattern, std::string inv)
 	bool return_status = false;
 
 	for (auto &it : cell_mappings) {
-		std::string from = it.first, to = it.first;
+		std::string from = it.first.str(), to = it.first.str();
 		if (from.size() != pattern.size())
 			continue;
 		for (size_t i = 0; i < from.size(); i++) {
diff --git a/passes/techmap/extract.cc b/passes/techmap/extract.cc
index 53bc00daf..6ebac265c 100644
--- a/passes/techmap/extract.cc
+++ b/passes/techmap/extract.cc
@@ -34,7 +34,7 @@ namespace
 	{
 	public:
 		bool ignore_parameters;
-		std::set<std::pair<std::string, std::string>> ignored_parameters;
+		std::set<std::pair<RTLIL::IdString, RTLIL::IdString>> ignored_parameters;
 		std::set<RTLIL::IdString> cell_attr, wire_attr;
 
 		SubCircuitSolver() : ignore_parameters(false)
@@ -106,10 +106,10 @@ namespace
 			if (!ignore_parameters) {
 				std::map<RTLIL::IdString, RTLIL::Const> needle_param, haystack_param;
 				for (auto &it : needleCell->parameters)
-					if (!ignored_parameters.count(std::pair<std::string, std::string>(needleCell->type, it.first)))
+					if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(needleCell->type, it.first)))
 						needle_param[it.first] = unified_param(needleCell->type, it.first, it.second);
 				for (auto &it : haystackCell->parameters)
-					if (!ignored_parameters.count(std::pair<std::string, std::string>(haystackCell->type, it.first)))
+					if (!ignored_parameters.count(std::pair<RTLIL::IdString, RTLIL::IdString>(haystackCell->type, it.first)))
 						haystack_param[it.first] = unified_param(haystackCell->type, it.first, it.second);
 				if (needle_param != haystack_param)
 					return false;
@@ -127,7 +127,7 @@ namespace
 				for (auto &conn : needleCell->connections())
 				{
 					RTLIL::SigSpec needleSig = conn.second;
-					RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first));
+					RTLIL::SigSpec haystackSig = haystackCell->getPort(portMapping.at(conn.first.str()));
 
 					for (int i = 0; i < std::min(needleSig.size(), haystackSig.size()); i++) {
 						RTLIL::Wire *needleWire = needleSig[i].wire, *haystackWire = haystackSig[i].wire;
@@ -201,14 +201,14 @@ namespace
 			if (sel && !sel->selected(mod, cell))
 				continue;
 
-			std::string type = cell->type;
+			std::string type = cell->type.str();
 			if (sel == NULL && type.substr(0, 2) == "\\$")
 				type = type.substr(1);
-			graph.createNode(cell->name, type, (void*)cell);
+			graph.createNode(cell->name.str(), type, (void*)cell);
 
 			for (auto &conn : cell->connections())
 			{
-				graph.createPort(cell->name, conn.first, conn.second.size());
+				graph.createPort(cell->name.str(), conn.first.str(), conn.second.size());
 
 				if (split && split->count(std::pair<RTLIL::IdString, RTLIL::IdString>(cell->type, conn.first)) > 0)
 					continue;
@@ -226,9 +226,9 @@ namespace
 							if (bit == RTLIL::State::S0) node = "$const$0";
 							if (bit == RTLIL::State::S1) node = "$const$1";
 							if (bit == RTLIL::State::Sz) node = "$const$z";
-							graph.createConnection(cell->name, conn.first, i, node, "\\Y", 0);
+							graph.createConnection(cell->name.str(), conn.first.str(), i, node, "\\Y", 0);
 						} else
-							graph.createConstant(cell->name, conn.first, i, int(bit.data));
+							graph.createConstant(cell->name.str(), conn.first.str(), i, int(bit.data));
 						continue;
 					}
 
@@ -246,7 +246,7 @@ namespace
 					}
 
 					bit_ref_t &bit_ref = sig_bit_ref[bit];
-					graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name, conn.first, i);
+					graph.createConnection(bit_ref.cell, bit_ref.port, bit_ref.bit, cell->name.str(), conn.first.str(), i);
 				}
 			}
 		}
@@ -293,7 +293,7 @@ namespace
 	RTLIL::Cell *replace(RTLIL::Module *needle, RTLIL::Module *haystack, SubCircuit::Solver::Result &match)
 	{
 		SigMap sigmap(needle);
-		SigSet<std::pair<std::string, int>> sig2port;
+		SigSet<std::pair<RTLIL::IdString, int>> sig2port;
 
 		// create new cell
 		RTLIL::Cell *cell = haystack->addCell(stringf("$extract$%s$%d", needle->name.c_str(), autoidx++), needle->name);
@@ -303,7 +303,7 @@ namespace
 			RTLIL::Wire *wire = it.second;
 			if (wire->port_id > 0) {
 				for (int i = 0; i < wire->width; i++)
-					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<std::string, int>(wire->name, i));
+					sig2port.insert(sigmap(RTLIL::SigSpec(wire, i)), std::pair<RTLIL::IdString, int>(wire->name, i));
 				cell->setPort(wire->name, RTLIL::SigSpec(RTLIL::State::Sz, wire->width));
 			}
 		}
@@ -320,10 +320,10 @@ namespace
 
 			for (auto &conn : needle_cell->connections()) {
 				RTLIL::SigSpec sig = sigmap(conn.second);
-				if (mapping.portMapping.count(conn.first) > 0 && sig2port.has(sigmap(sig))) {
+				if (mapping.portMapping.count(conn.first.str()) > 0 && sig2port.has(sigmap(sig))) {
 					for (int i = 0; i < sig.size(); i++)
 					for (auto &port : sig2port.find(sig[i])) {
-						RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first]).extract(i, 1);
+						RTLIL::SigSpec bitsig = haystack_cell->getPort(mapping.portMapping[conn.first.str()]).extract(i, 1);
 						RTLIL::SigSpec new_sig = cell->getPort(port.first);
 						new_sig.replace(port.second, bitsig);
 						cell->setPort(port.first, new_sig);
@@ -561,7 +561,7 @@ struct ExtractPass : public Pass {
 				continue;
 			}
 			if (args[argidx] == "-ignore_param" && argidx+2 < args.size()) {
-				solver.ignored_parameters.insert(std::pair<std::string, std::string>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
+				solver.ignored_parameters.insert(std::pair<RTLIL::IdString, RTLIL::IdString>(RTLIL::escape_id(args[argidx+1]), RTLIL::escape_id(args[argidx+2])));
 				argidx += 2;
 				continue;
 			}
diff --git a/passes/techmap/simplemap.cc b/passes/techmap/simplemap.cc
index f1f334f6e..960578b06 100644
--- a/passes/techmap/simplemap.cc
+++ b/passes/techmap/simplemap.cc
@@ -24,7 +24,7 @@
 #include <stdio.h>
 #include <string.h>
 
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
 
 static void simplemap_not(RTLIL::Module *module, RTLIL::Cell *cell)
 {
@@ -382,7 +382,7 @@ static void simplemap_dlatch(RTLIL::Module *module, RTLIL::Cell *cell)
 	}
 }
 
-void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
+void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers)
 {
 	mappers["$not"]         = simplemap_not;
 	mappers["$pos"]         = simplemap_pos;
@@ -431,7 +431,7 @@ struct SimplemapPass : public Pass {
 		log_header("Executing SIMPLEMAP pass (map simple cells to gate primitives).\n");
 		extra_args(args, 1, design);
 
-		std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
+		std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> mappers;
 		simplemap_get_mappers(mappers);
 
 		for (auto mod : design->modules()) {
diff --git a/passes/techmap/techmap.cc b/passes/techmap/techmap.cc
index 1f812e52f..2bcd3003e 100644
--- a/passes/techmap/techmap.cc
+++ b/passes/techmap/techmap.cc
@@ -29,7 +29,7 @@
 #include "passes/techmap/techmap.inc"
 
 // see simplemap.cc
-extern void simplemap_get_mappers(std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
+extern void simplemap_get_mappers(std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> &mappers);
 
 static void apply_prefix(std::string prefix, std::string &id)
 {
@@ -44,7 +44,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 	std::vector<RTLIL::SigChunk> chunks = sig;
 	for (auto &chunk : chunks)
 		if (chunk.wire != NULL) {
-			std::string wire_name = chunk.wire->name;
+			std::string wire_name = chunk.wire->name.str();
 			apply_prefix(prefix, wire_name);
 			log_assert(module->wires_.count(wire_name) > 0);
 			chunk.wire = module->wires_[wire_name];
@@ -54,7 +54,7 @@ static void apply_prefix(std::string prefix, RTLIL::SigSpec &sig, RTLIL::Module
 
 struct TechmapWorker
 {
-	std::map<std::string, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
+	std::map<RTLIL::IdString, void(*)(RTLIL::Module*, RTLIL::Cell*)> simplemap_mappers;
 	std::map<std::pair<RTLIL::IdString, std::map<RTLIL::IdString, RTLIL::Const>>, RTLIL::Module*> techmap_cache;
 	std::map<RTLIL::Module*, bool> techmap_do_cache;
 	std::set<RTLIL::Module*> module_queue;
@@ -80,7 +80,7 @@ struct TechmapWorker
 	std::string constmap_tpl_name(SigMap &sigmap, RTLIL::Module *tpl, RTLIL::Cell *cell, bool verbose)
 	{
 		std::string constmap_info;
-		std::map<RTLIL::SigBit, std::pair<std::string, int>> connbits_map;
+		std::map<RTLIL::SigBit, std::pair<RTLIL::IdString, int>> connbits_map;
 
 		for (auto conn : cell->connections())
 			for (int i = 0; i < SIZE(conn.second); i++) {
@@ -96,7 +96,7 @@ struct TechmapWorker
 					constmap_info += stringf("|%s %d %s %d", log_id(conn.first), i,
 							log_id(connbits_map.at(bit).first), connbits_map.at(bit).second);
 				} else
-					connbits_map[bit] = std::pair<std::string, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
+					connbits_map[bit] = std::pair<RTLIL::IdString, int>(conn.first, i);stringf("%s %d", log_id(conn.first), i, bit.data);
 			}
 
 		return stringf("$paramod$constmap:%s%s", sha1(constmap_info).c_str(), tpl->name.c_str());
@@ -156,7 +156,7 @@ struct TechmapWorker
 			for (auto &it : tpl->cells_)
 				if (it.first == "\\_TECHMAP_REPLACE_") {
 					orig_cell_name = cell->name;
-					module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name);
+					module->rename(cell, stringf("$techmap%d", autoidx++) + cell->name.str());
 					break;
 				}
 
@@ -165,8 +165,8 @@ struct TechmapWorker
 		for (auto &it : tpl->wires_) {
 			if (it.second->port_id > 0)
 				positional_ports[stringf("$%d", it.second->port_id)] = it.first;
-			std::string w_name = it.second->name;
-			apply_prefix(cell->name, w_name);
+			std::string w_name = it.second->name.str();
+			apply_prefix(cell->name.str(), w_name);
 			RTLIL::Wire *w = module->addWire(w_name, it.second);
 			w->port_input = false;
 			w->port_output = false;
@@ -192,11 +192,11 @@ struct TechmapWorker
 			if (w->port_output) {
 				c.first = it.second;
 				c.second = RTLIL::SigSpec(w);
-				apply_prefix(cell->name, c.second, module);
+				apply_prefix(cell->name.str(), c.second, module);
 			} else {
 				c.first = RTLIL::SigSpec(w);
 				c.second = it.second;
-				apply_prefix(cell->name, c.first, module);
+				apply_prefix(cell->name.str(), c.first, module);
 			}
 			if (c.second.size() > c.first.size())
 				c.second.remove(c.first.size(), c.second.size() - c.first.size());
@@ -219,12 +219,12 @@ struct TechmapWorker
 
 		for (auto &it : tpl->cells_)
 		{
-			RTLIL::IdString c_name = it.second->name;
+			std::string c_name = it.second->name.str();
 
 			if (!flatten_mode && c_name == "\\_TECHMAP_REPLACE_")
 				c_name = orig_cell_name;
 			else
-				apply_prefix(cell->name, c_name);
+				apply_prefix(cell->name.str(), c_name);
 
 			RTLIL::Cell *c = module->addCell(c_name, it.second);
 			design->select(module, c);
@@ -233,15 +233,15 @@ struct TechmapWorker
 				c->type = c->type.substr(1);
 
 			for (auto &it2 : c->connections_) {
-				apply_prefix(cell->name, it2.second, module);
+				apply_prefix(cell->name.str(), it2.second, module);
 				port_signal_map.apply(it2.second);
 			}
 		}
 
 		for (auto &it : tpl->connections()) {
 			RTLIL::SigSig c = it;
-			apply_prefix(cell->name, c.first, module);
-			apply_prefix(cell->name, c.second, module);
+			apply_prefix(cell->name.str(), c.first, module);
+			apply_prefix(cell->name.str(), c.second, module);
 			port_signal_map.apply(c.first);
 			port_signal_map.apply(c.second);
 			module->connect(c);
@@ -271,7 +271,7 @@ struct TechmapWorker
 				continue;
 
 			if (celltypeMap.count(cell->type) == 0) {
-				if (assert_mode && cell->type.back() != '_')
+				if (assert_mode && cell->type.str().back() != '_')
 					log_error("(ASSERT MODE) No matching template cell for type %s found.\n", log_id(cell->type));
 				continue;
 			}
@@ -313,7 +313,7 @@ struct TechmapWorker
 
 			for (auto &tpl_name : celltypeMap.at(cell->type))
 			{
-				std::string derived_name = tpl_name;
+				RTLIL::IdString derived_name = tpl_name;
 				RTLIL::Module *tpl = map->modules_[tpl_name];
 				std::map<RTLIL::IdString, RTLIL::Const> parameters = cell->parameters;
 
@@ -499,7 +499,7 @@ struct TechmapWorker
 									if (!wire->port_input || wire->port_output)
 										continue;
 
-									std::string port_name = wire->name;
+									RTLIL::IdString port_name = wire->name;
 									tpl->rename(wire, NEW_ID);
 
 									RTLIL::Wire *new_wire = tpl->addWire(port_name, wire);
diff --git a/passes/tests/test_autotb.cc b/passes/tests/test_autotb.cc
index 844bcbc9c..d26002277 100644
--- a/passes/tests/test_autotb.cc
+++ b/passes/tests/test_autotb.cc
@@ -109,8 +109,8 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 			RTLIL::Wire *wire = it2->second;
 			if (wire->port_output) {
 				count_ports++;
-				signal_out[idy("sig", mod->name, wire->name)] = wire->width;
-				fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
+				signal_out[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
+				fprintf(f, "wire [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 			} else if (wire->port_input) {
 				count_ports++;
 				bool is_clksignal = wire->get_bool_attribute("\\gentb_clock");
@@ -124,25 +124,25 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 							is_clksignal = true;
 				}
 				if (is_clksignal && wire->attributes.count("\\gentb_constant") == 0) {
-					signal_clk[idy("sig", mod->name, wire->name)] = wire->width;
+					signal_clk[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 				} else {
-					signal_in[idy("sig", mod->name, wire->name)] = wire->width;
+					signal_in[idy("sig", mod->name.str(), wire->name.str())] = wire->width;
 					if (wire->attributes.count("\\gentb_constant") != 0)
-						signal_const[idy("sig", mod->name, wire->name)] = wire->attributes["\\gentb_constant"].as_string();
+						signal_const[idy("sig", mod->name.str(), wire->name.str())] = wire->attributes["\\gentb_constant"].as_string();
 				}
-				fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name, wire->name).c_str());
+				fprintf(f, "reg [%d:0] %s;\n", wire->width-1, idy("sig", mod->name.str(), wire->name.str()).c_str());
 			}
 		}
-		fprintf(f, "%s %s(\n", id(mod->name).c_str(), idy("uut", mod->name).c_str());
+		fprintf(f, "%s %s(\n", id(mod->name.str()).c_str(), idy("uut", mod->name.str()).c_str());
 		for (auto it2 = mod->wires_.begin(); it2 != mod->wires_.end(); it2++) {
 			RTLIL::Wire *wire = it2->second;
 			if (wire->port_output || wire->port_input)
-				fprintf(f, "\t.%s(%s)%s\n", id(wire->name).c_str(),
-						idy("sig", mod->name, wire->name).c_str(), --count_ports ? "," : "");
+				fprintf(f, "\t.%s(%s)%s\n", id(wire->name.str()).c_str(),
+						idy("sig", mod->name.str(), wire->name.str()).c_str(), --count_ports ? "," : "");
 		}
 		fprintf(f, ");\n\n");
 
-		fprintf(f, "task %s;\n", idy(mod->name, "reset").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "reset").c_str());
 		fprintf(f, "begin\n");
 		int delay_counter = 0;
 		for (auto it = signal_in.begin(); it != signal_in.end(); it++)
@@ -169,7 +169,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 		fprintf(f, "end\n");
 		fprintf(f, "endtask\n\n");
 
-		fprintf(f, "task %s;\n", idy(mod->name, "update_data").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "update_data").c_str());
 		fprintf(f, "begin\n");
 		delay_counter = 0;
 		for (auto it = signal_in.begin(); it != signal_in.end(); it++) {
@@ -181,7 +181,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 		fprintf(f, "end\n");
 		fprintf(f, "endtask\n\n");
 
-		fprintf(f, "task %s;\n", idy(mod->name, "update_clock").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "update_clock").c_str());
 		fprintf(f, "begin\n");
 		if (signal_clk.size()) {
 			fprintf(f, "\txorshift128;\n");
@@ -203,7 +203,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 		std::vector<std::string> header1;
 		std::string header2 = "";
 
-		fprintf(f, "task %s;\n", idy(mod->name, "print_status").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "print_status").c_str());
 		fprintf(f, "begin\n");
 		fprintf(f, "\t$display(\"#OUT# %%b %%b %%b %%t %%d\", {");
 		if (signal_in.size())
@@ -265,7 +265,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 		fprintf(f, "end\n");
 		fprintf(f, "endtask\n\n");
 
-		fprintf(f, "task %s;\n", idy(mod->name, "print_header").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "print_header").c_str());
 		fprintf(f, "begin\n");
 		fprintf(f, "\t$display(\"#OUT#\");\n");
 		for (auto &hdr : header1)
@@ -275,15 +275,15 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 		fprintf(f, "end\n");
 		fprintf(f, "endtask\n\n");
 
-		fprintf(f, "task %s;\n", idy(mod->name, "test").c_str());
+		fprintf(f, "task %s;\n", idy(mod->name.str(), "test").c_str());
 		fprintf(f, "begin\n");
-		fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name).c_str());
-		fprintf(f, "\t%s;\n", idy(mod->name, "reset").c_str());
+		fprintf(f, "\t$display(\"#OUT#\\n#OUT# ==== %s ====\");\n", idy(mod->name.str()).c_str());
+		fprintf(f, "\t%s;\n", idy(mod->name.str(), "reset").c_str());
 		fprintf(f, "\tfor (i=0; i<%d; i=i+1) begin\n", num_iter);
-		fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name, "print_header").c_str());
-		fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_data").c_str());
-		fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "update_clock").c_str());
-		fprintf(f, "\t\t#100; %s;\n", idy(mod->name, "print_status").c_str());
+		fprintf(f, "\t\tif (i %% 20 == 0) %s;\n", idy(mod->name.str(), "print_header").c_str());
+		fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_data").c_str());
+		fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "update_clock").c_str());
+		fprintf(f, "\t\t#100; %s;\n", idy(mod->name.str(), "print_status").c_str());
 		fprintf(f, "\tend\n");
 		fprintf(f, "end\n");
 		fprintf(f, "endtask\n\n");
@@ -294,7 +294,7 @@ static void autotest(FILE *f, RTLIL::Design *design, int num_iter)
 	fprintf(f, "\t// $dumpvars(0, testbench);\n");
 	for (auto it = design->modules_.begin(); it != design->modules_.end(); it++)
 		if (!it->second->get_bool_attribute("\\gentb_skip"))
-			fprintf(f, "\t%s;\n", idy(it->first, "test").c_str());
+			fprintf(f, "\t%s;\n", idy(it->first.str(), "test").c_str());
 	fprintf(f, "\t$finish;\n");
 	fprintf(f, "end\n\n");