From: Cesar Strauss Date: Fri, 2 Apr 2021 22:26:21 +0000 (-0300) Subject: End VL loop as soon as either src/dst step reaches VL X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9e5fcccef1b8f74ef1ae271fa7d7e4d92bb65e3;p=soc.git End VL loop as soon as either src/dst step reaches VL Also, avoid incrementing dststep beyond VL-1 --- diff --git a/src/soc/decoder/isa/caller.py b/src/soc/decoder/isa/caller.py index 95dc0f47..2c784b3c 100644 --- a/src/soc/decoder/isa/caller.py +++ b/src/soc/decoder/isa/caller.py @@ -979,7 +979,7 @@ class ISACaller: # check if end reached (we let srcstep overrun, above) # nothing needs doing (TODO zeroing): just do next instruction - if srcstep == vl: + if srcstep == vl or dststep == vl: self.svp64_reset_loop() self.update_pc_next() return @@ -1145,7 +1145,7 @@ class ISACaller: svp64_is_vector = (no_out_vec or no_in_vec) else: svp64_is_vector = no_out_vec - if svp64_is_vector and srcstep != vl-1: + if svp64_is_vector and srcstep != vl-1 and dststep != vl-1: self.svstate.srcstep += SelectableInt(1, 7) self.svstate.dststep += SelectableInt(1, 7) self.pc.NIA.value = self.pc.CIA.value