From: Jean THOMAS <git0@pub.jeanthomas.me>
Date: Wed, 10 Jun 2020 10:48:18 +0000 (+0200)
Subject: Add self._bridge to m.submodules (fixing #4)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9f83db94ca5d26646c0f57c3320666d5a5e724f;p=gram.git

Add self._bridge to m.submodules (fixing #4)
---

diff --git a/gram/core/__init__.py b/gram/core/__init__.py
index 5a07556..16b022e 100644
--- a/gram/core/__init__.py
+++ b/gram/core/__init__.py
@@ -52,6 +52,8 @@ class gramCore(Peripheral, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        m.submodules += self._bridge
+
         m.submodules += self.dfii
         m.d.comb += self.dfii.master.connect(self._phy.dfi)
 
diff --git a/gram/phy/ecp5ddrphy.py b/gram/phy/ecp5ddrphy.py
index 6e1ec04..cf1a9c9 100644
--- a/gram/phy/ecp5ddrphy.py
+++ b/gram/phy/ecp5ddrphy.py
@@ -155,6 +155,8 @@ class ECP5DDRPHY(Peripheral, Elaboratable):
     def elaborate(self, platform):
         m = Module()
 
+        m.submodules += self._bridge
+
         tck = 2/(2*2*self._sys_clk_freq)
         nphases = 2
         databits = len(self.pads.dq.oe)