From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Thu, 21 Mar 2019 20:05:11 +0000 (+0000)
Subject: whitespace cleanup
X-Git-Tag: ls180-24jan2020~1548
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9f9904b92e0d630bb43437b2971ad28b37b51f2;p=ieee754fpu.git

whitespace cleanup
---

diff --git a/src/add/nmigen_add_experiment.py b/src/add/nmigen_add_experiment.py
index bf21cf57..dd7b4911 100644
--- a/src/add/nmigen_add_experiment.py
+++ b/src/add/nmigen_add_experiment.py
@@ -170,7 +170,6 @@ class FPGetOp(FPState):
         """
         setattr(m.submodules, self.state_from, self.mod)
         m.d.comb += self.mod.in_op.eq(in_op)
-        #m.d.comb += self.out_op.eq(self.mod.out_op)
         m.d.comb += self.out_decode.eq(self.mod.out_decode)
 
     def action(self, m):
@@ -200,7 +199,6 @@ class FPGet2OpMod(Trigger):
 
     def elaborate(self, platform):
         m = Trigger.elaborate(self, platform)
-        #m.submodules.get_op_in = self.in_op
         m.submodules.get_op1_out = self.o.a
         m.submodules.get_op2_out = self.o.b
         out_op1 = FPNumIn(None, self.width)
@@ -1773,6 +1771,7 @@ class FPADDBase(FPState, FPID):
             with m.Else():
                 m.d.sync += self.out_z.stb.eq(1)
 
+
 class ResArray:
     def __init__(self, width, id_wid):
         self.width = width