From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 24 Apr 2021 13:43:30 +0000 (+0000)
Subject: correct relative link to FreePDK45_c4m45, use submodule
X-Git-Tag: LS180_RC3~88
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=b9fb3a330b3900a23edef0319449f3344418a156;p=soclayout.git

correct relative link to FreePDK45_c4m45, use submodule
add note about remembering to run git submodule
---

diff --git a/experiments10_verilog/freepdk_c4m45/Makefile b/experiments10_verilog/freepdk_c4m45/Makefile
index e86078c..96c5924 100755
--- a/experiments10_verilog/freepdk_c4m45/Makefile
+++ b/experiments10_verilog/freepdk_c4m45/Makefile
@@ -1,5 +1,7 @@
 
-            PDKMASTER_TOP = $(shell pwd)/../../../c4m-pdk-freepdk45
+            # use git submodule version of c4m-pdk-freepdk45
+	    # remember to do "git submodule update --init --remote
+            PDKMASTER_TOP = $(shell pwd)/../../c4m-pdk-freepdk45
         LOGICAL_SYNTHESIS = Yosys
        PHYSICAL_SYNTHESIS = Coriolis
                DESIGN_KIT = FreePDK_C4M45
diff --git a/experiments10_verilog/freepdk_c4m45/build_full.sh b/experiments10_verilog/freepdk_c4m45/build_full.sh
index 67dd695..5dde008 100755
--- a/experiments10_verilog/freepdk_c4m45/build_full.sh
+++ b/experiments10_verilog/freepdk_c4m45/build_full.sh
@@ -5,8 +5,8 @@
 # change the settings to the larger chip/corona size
 echo "remember to check doDesign core size"
 
-pdk=`realpath ../../c4m-pdk-freepdk45`
-export NDA_TOP=${pdk}/coriolis/techno
+export PDKMASTER_TOP=`realpath ../../c4m-pdk-freepdk45`
+export NDA_TOP=${FREEPDK45_C4M}/coriolis/techno
 
 # initialise/update the pinmux & c4m-pdk-freepdk45 submodule
 #pushd ..
@@ -16,11 +16,6 @@ git submodule update --init --remote
 # makes symlinks to alliance
 ./mksym.sh
 touch mk/users.d/user-${USER}.mk
-rm -f mk/design-flow.mk
-cp design-flow.mk mk/
-lib=${pdk}/views/FreePDK45/FlexLib/liberty/FlexLib_nom.lib
-echo "export REAL_MODE = Yes" > mk/dks.d/FreePDK_C4M45.mk
-echo "export LIBERTY_FILE = $lib" >> mk/dks.d/FreePDK_C4M45.mk
 
 # clear out
 make clean
diff --git a/experiments10_verilog/freepdk_c4m45/mksym.sh b/experiments10_verilog/freepdk_c4m45/mksym.sh
index 1659db8..a458171 100755
--- a/experiments10_verilog/freepdk_c4m45/mksym.sh
+++ b/experiments10_verilog/freepdk_c4m45/mksym.sh
@@ -24,6 +24,7 @@ for script in "${ScriptsArray[@]}"; do
 done
 
 declare -a LibsArray=("sxlib" "nsxlib" "nsxlib45" "cmos" "cmos45" "mosis"
+	 	      "FreePDK_45" "FreePDK_C4M45"
 )
 
 for script in "${LibsArray[@]}"; do