From: Tim 'mithro' Ansell <me@mith.ro>
Date: Sat, 27 Oct 2018 23:02:53 +0000 (-0700)
Subject: uart: Enable buffering the FIFO.
X-Git-Tag: 24jan2021_ls180~1556^2
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba0dd5728e04d4c24e67354304c70d29f96dfd20;p=litex.git

uart: Enable buffering the FIFO.

On the iCE40 FPGA, adding buffering allows the SyncFIFO to be placed in
block RAM rather than consuming a large amount of resources.
---

diff --git a/litex/soc/cores/uart.py b/litex/soc/cores/uart.py
index 3e88e7ae..a5305e6a 100644
--- a/litex/soc/cores/uart.py
+++ b/litex/soc/cores/uart.py
@@ -157,7 +157,7 @@ def _get_uart_fifo(depth, sink_cd="sys", source_cd="sys"):
         fifo = stream.AsyncFIFO([("data", 8)], depth)
         return ClockDomainsRenamer({"write": sink_cd, "read": source_cd})(fifo)
     else:
-        return stream.SyncFIFO([("data", 8)], depth)
+        return stream.SyncFIFO([("data", 8)], depth, buffered=True)
 
 
 class UART(Module, AutoCSR):