From: lkcl <lkcl@web>
Date: Thu, 30 Mar 2023 00:10:39 +0000 (+0100)
Subject: (no commit message)
X-Git-Tag: opf_rfc_ls012_v1~216
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba10c1a424d77f93a5125878fa779b5504142c10;p=libreriscv.git

---

diff --git a/openpower/sv/rfc/ls010.mdwn b/openpower/sv/rfc/ls010.mdwn
index 3ed1b9876..41b01a266 100644
--- a/openpower/sv/rfc/ls010.mdwn
+++ b/openpower/sv/rfc/ls010.mdwn
@@ -1152,6 +1152,7 @@ which creates scenarios unique to Vector applications, that a Scalar
 (and even a SIMD) ISA simply never encounters.  SVP64 endeavours to add
 the modes typically found in *all* Scalable Vector ISAs, without changing
 the behaviour of the underlying Base (Scalar) v3.0B operations in any way.
+(The sole apparent exception is Post-Increment Mode on LD/ST-update instructions)
 
 ## Modes overview