From: lkcl Date: Thu, 24 Dec 2020 06:20:25 +0000 (+0000) Subject: (no commit message) X-Git-Tag: convert-csv-opcode-to-binary~979 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba1e5d7f5081fa4b1d8d0f432fc900f73bb84a8f;p=libreriscv.git --- diff --git a/openpower/sv/overview.mdwn b/openpower/sv/overview.mdwn index 127f9203b..acc50ef64 100644 --- a/openpower/sv/overview.mdwn +++ b/openpower/sv/overview.mdwn @@ -25,7 +25,11 @@ In OpenPOWER ISA v3.0B pseudo-code form, an ADD operation, assuming both source for i = 0 to VL-1: GPR(RT+i) = GPR(RA+i) + GPR(RB+i) -At its heart, SimpleV really is this simple. On top of this fundamental basis further subtle refinements can be added which build up towards an extremrly powerful Vector augmentation system, with very little in the way of additional opcodes required. RISC-V RVV as of version 0.9 is over 180 instructions: over 95% of rhat functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions. +At its heart, SimpleV really is this simple. On top of this fundamental basis further subtle refinements can be added which build up towards an extremely powerful Vector augmentation system, with very little in the way of additional opcodes required. + +RISC-V RVV as of version 0.9 is over 180 instructions (more than the rest of RV64G combined). Over 95% of that functionality is added to OpenPOWER v3 0B, by SimpleV augmentation, with around 5 to 8 instructions. + +Even in OpenPOWER v3.0B, the Scalar Integer ISA is around 150 instructions, with IEEE754 FP adding approximately 80 more. VSX, being based on SIMD design principles, adds somewhere in the region of 600 more.