From: Eddie Hung <eddie@fpgeh.com>
Date: Mon, 19 Aug 2019 18:18:33 +0000 (-0700)
Subject: Move from cell attr to module attr
X-Git-Tag: working-ls180~881^2^2~243
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba2261e21a18b969473f228b5f55bd5612558ed8;p=yosys.git

Move from cell attr to module attr
---

diff --git a/passes/techmap/abc9.cc b/passes/techmap/abc9.cc
index 398df190c..be2a8d50b 100644
--- a/passes/techmap/abc9.cc
+++ b/passes/techmap/abc9.cc
@@ -1202,7 +1202,15 @@ struct Abc9Pass : public Pass {
 			std::map<RTLIL::SigBit, std::set<RTLIL::Cell*>> bit_to_cell, bit_to_cell_up, bit_to_cell_down;
 
 			pool<IdString> seen_cells;
-			dict<IdString, std::pair<RTLIL::IdString,RTLIL::IdString>> flop_data;
+			struct flop_data_t {
+				IdString clk_port;
+				IdString clk_pol_param;
+				bool clk_pol;
+				IdString en_port;
+				IdString en_pol_param;
+				bool en_pol;
+			};
+			dict<IdString, flop_data_t> flop_data;
 
 			for (auto cell : all_cells) {
 				clkdomain_t key;
@@ -1253,7 +1261,40 @@ struct Abc9Pass : public Pass {
 						log_error("'abc_flop_clk' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
 					if (abc_flop_en == IdString())
 						log_error("'abc_flop_en' attribute not found on any ports on module '%s'.\n", log_id(cell->type));
-					it = flop_data.insert(std::make_pair(cell->type, std::make_pair(abc_flop_clk, abc_flop_en))).first;
+
+					auto jt = inst_module->attributes.find("\\abc_flop_clk_pol");
+					if (jt == inst_module->attributes.end())
+						log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(inst_module));
+					IdString abc_flop_clk_pol_param;
+					bool abc_flop_clk_pol;
+					if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
+						auto param = jt->second.decode_string();
+						abc_flop_clk_pol = (param[0] == '!');
+						if (abc_flop_clk_pol)
+							abc_flop_clk_pol_param = RTLIL::escape_id(param.substr(1));
+						else
+							abc_flop_clk_pol_param = RTLIL::escape_id(param);
+					}
+					else
+						abc_flop_clk_pol = !jt->second.as_bool();
+					jt = inst_module->attributes.find("\\abc_flop_en_pol");
+					if (jt == inst_module->attributes.end())
+						log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(inst_module));
+					IdString abc_flop_en_pol_param;
+					bool abc_flop_en_pol;
+					if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
+						auto param = jt->second.decode_string();
+						abc_flop_en_pol = (param[0] == '!');
+						if (abc_flop_en_pol)
+							abc_flop_en_pol_param = RTLIL::escape_id(param.substr(1));
+						else
+							abc_flop_en_pol_param = RTLIL::escape_id(param);
+					}
+					else
+						abc_flop_en_pol = !jt->second.as_bool();
+
+					it = flop_data.insert(std::make_pair(cell->type, flop_data_t{abc_flop_clk, abc_flop_clk_pol_param, abc_flop_clk_pol,
+								abc_flop_en, abc_flop_en_pol_param, abc_flop_en_pol})).first;
 				}
 				else {
 					it = flop_data.find(cell->type);
@@ -1261,35 +1302,34 @@ struct Abc9Pass : public Pass {
 						continue;
 				}
 
-				auto jt = cell->attributes.find("\\abc_flop_clk_pol");
-				if (jt == cell->parameters.end())
-					log_error("'abc_flop_clk_pol' attribute not found on module '%s'.\n", log_id(cell->type));
+				const auto &data = it->second;
+
 				bool this_clk_pol;
-				if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
-					auto param = jt->second.decode_string();
-					auto kt = cell->parameters.find(param);
-					if (kt == cell->parameters.end())
+				if (data.clk_pol_param == IdString())
+					this_clk_pol = data.clk_pol;
+				else {
+					auto param = data.clk_pol_param;
+					auto jt = cell->parameters.find(param);
+					if (jt == cell->parameters.end())
 						log_error("'abc_flop_clk_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
-					this_clk_pol = kt->second.as_bool();
-				}
-				else
 					this_clk_pol = jt->second.as_bool();
-				jt = cell->parameters.find("\\$abc_flop_en_pol");
-				if (jt == cell->parameters.end())
-					log_error("'abc_flop_en_pol' attribute not found on module '%s'.\n", log_id(cell->type));
+					if (data.clk_pol)
+						this_clk_pol = !this_clk_pol;
+				}
 				bool this_en_pol;
-				if (jt->second.flags == RTLIL::ConstFlags::CONST_FLAG_STRING) {
-					auto param = jt->second.decode_string();
-					auto kt = cell->parameters.find(param);
-					if (kt == cell->parameters.end())
+				if (data.en_pol_param == IdString())
+					this_en_pol = data.en_pol;
+				else {
+					auto param = data.en_pol_param;
+					auto jt = cell->parameters.find(param);
+					if (jt == cell->parameters.end())
 						log_error("'abc_flop_en_pol' value '%s' is not a parameter on module '%s'.\n", param.c_str(), log_id(cell->type));
-					this_en_pol = kt->second.as_bool();
-				}
-				else
 					this_en_pol = jt->second.as_bool();
+					if (data.en_pol)
+						this_en_pol = !this_en_pol;
+				}
 
-				const auto &data = it->second;
-				key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.first)), this_en_pol, assign_map(cell->getPort(data.second)));
+				key = clkdomain_t(this_clk_pol, assign_map(cell->getPort(data.clk_port)), this_en_pol, assign_map(cell->getPort(data.en_port)));
 
 				unassigned_cells.erase(cell);
 				expand_queue.insert(cell);
diff --git a/techlibs/xilinx/abc_ff.v b/techlibs/xilinx/abc_ff.v
index 1d308fa96..117820f0d 100644
--- a/techlibs/xilinx/abc_ff.v
+++ b/techlibs/xilinx/abc_ff.v
@@ -26,7 +26,6 @@ module FDRE (output reg Q, input C, CE, D, R);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_R_INVERTED = 1'b0;
   wire \$nextQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDRE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -40,7 +39,6 @@ endmodule
 module FDRE_1 (output reg Q, input C, CE, D, R);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDRE_1 #(.INIT(|0)
   ) _TECHMAP_REPLACE_ (
     .D(D), .Q(\$nextQ ), .\$pastQ (Q), .C(C), .CE(CE), .R(R)
@@ -54,7 +52,6 @@ module FDCE (output reg Q, input C, CE, D, CLR);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_CLR_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDCE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -69,7 +66,6 @@ endmodule
 module FDCE_1 (output reg Q, input C, CE, D, CLR);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDCE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -85,7 +81,6 @@ module FDPE (output reg Q, input C, CE, D, PRE);
   parameter [0:0] IS_D_INVERTED = 1'b0;
   parameter [0:0] IS_PRE_INVERTED = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
   \$__ABC_FDPE #(
     .INIT(INIT),
     .IS_C_INVERTED(IS_C_INVERTED),
@@ -100,7 +95,6 @@ endmodule
 module FDPE_1 (output reg Q, input C, CE, D, PRE);
   parameter [0:0] INIT = 1'b0;
   wire \$nextQ , \$currQ ;
-  (* abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
   \$__ABC_FDPE_1 #(
     .INIT(INIT)
   ) _TECHMAP_REPLACE_ (
@@ -118,7 +112,7 @@ endmodule
 module \$__ABC_ASYNC (input A, S, output Y);
 endmodule
 
-(* abc_box_id = 1001, lib_whitebox, abc_flop = "FDRE" *)
+(* abc_box_id=1001, lib_whitebox, abc_flop="FDRE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -131,7 +125,7 @@ module \$__ABC_FDRE ((* abc_flop_q *)   output Q,
   assign Q = (R ^ IS_R_INVERTED) ? 1'b0 : (CE ? (D ^ IS_D_INVERTED) : \$pastQ );
 endmodule
 
-(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1" *)
+(* abc_box_id = 1002, lib_whitebox, abc_flop = "FDRE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
@@ -141,7 +135,7 @@ module \$__ABC_FDRE_1 ((* abc_flop_q *)   output Q,
   assign Q = R ? 1'b0 : (CE ? D : \$pastQ );
 endmodule
 
-(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE" *)
+(* abc_box_id = 1003, lib_whitebox, abc_flop = "FDCE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -154,7 +148,7 @@ module \$__ABC_FDCE ((* abc_flop_q *)   output Q,
   assign Q = (CE && !(CLR ^ IS_CLR_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1" *)
+(* abc_box_id = 1004, lib_whitebox, abc_flop = "FDCE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,
@@ -164,7 +158,7 @@ module \$__ABC_FDCE_1 ((* abc_flop_q *)   output Q,
   assign Q = (CE && !CLR) ? D : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1005, lib_whitebox, abc_flop = "FDPE" *)
+(* abc_box_id=1005, lib_whitebox, abc_flop="FDPE", abc_flop_clk_pol="!IS_C_INVERTED", abc_flop_en_pol=1 *)
 module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
                      (* abc_flop_clk *) input C,
                      (* abc_flop_en *)  input CE,
@@ -177,7 +171,7 @@ module \$__ABC_FDPE ((* abc_flop_q *)   output Q,
   assign Q = (CE && !(PRE ^ IS_PRE_INVERTED)) ? (D ^ IS_D_INVERTED) : \$pastQ ;
 endmodule
 
-(* abc_box_id = 1006, lib_whitebox, abc_flop = "FDPE_1" *)
+(* abc_box_id=1006, lib_whitebox, abc_flop="FDPE_1", abc_flop_clk_pol=1, abc_flop_en_pol=1 *)
 module \$__ABC_FDPE_1 ((* abc_flop_q *)   output Q,
                        (* abc_flop_clk *) input C,
                        (* abc_flop_en *)  input CE,