From: Florent Kermarrec Date: Mon, 14 Oct 2019 07:12:25 +0000 (+0200) Subject: integration/soc_core: expose more SoC parameters X-Git-Tag: 24jan2021_ls180~908 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba26441889ee0b24743eb55f32c74daab246555e;p=litex.git integration/soc_core: expose more SoC parameters --- diff --git a/litex/build/xilinx/vivado.py b/litex/build/xilinx/vivado.py index 1be23874..9e307518 100644 --- a/litex/build/xilinx/vivado.py +++ b/litex/build/xilinx/vivado.py @@ -278,7 +278,7 @@ class XilinxVivadoToolchain: self.false_paths.add((from_, to)) def vivado_build_args(parser): - parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys)") + parser.add_argument("--synth-mode", default="vivado", help="synthesis mode (vivado or yosys, default=vivado)") def vivado_build_argdict(args): diff --git a/litex/soc/integration/soc_core.py b/litex/soc/integration/soc_core.py index ef9854a7..63db68e7 100644 --- a/litex/soc/integration/soc_core.py +++ b/litex/soc/integration/soc_core.py @@ -513,17 +513,47 @@ class SoCCore(Module): # SoCCore arguments -------------------------------------------------------------------------------- def soc_core_args(parser): + # CPU parameters parser.add_argument("--cpu-type", default=None, help="select CPU: {}".format(", ".join(iter(cpu.CPUS.keys())))) parser.add_argument("--cpu-variant", default=None, - help="select CPU variant") + help="select CPU variant, (default=standard)") + parser.add_argument("--cpu-reset-address", default=None, type=int, + help="CPU reset address (default=0x00000000 or ROM)") + # ROM parameters parser.add_argument("--integrated-rom-size", default=None, type=int, help="size/enable the integrated (BIOS) ROM") + # SRAM parameters + parser.add_argument("--integrated_sram_size", default=None, + help="size/enable the integrated SRAM") + # MAIN_RAM parameters parser.add_argument("--integrated-main-ram-size", default=None, type=int, help="size/enable the integrated main RAM") + # CSR parameters + parser.add_argument("--csr-data-width", default=None, type=int, + help="CSR bus data-width (8 or 32, default=8)") + parser.add_argument("--csr-address-width", default=14, type=int, + help="CSR bus address-width") + # Identifier parameters + parser.add_argument("--ident", default=None, type=str, + help="SoC identifier (default=\"\"") + parser.add_argument("--ident-version", default=None, type=bool, + help="add date/time to SoC identifier (default=False)") + # UART parameters + parser.add_argument("--with-uart", default=None, type=bool, + help="with UART (default=True)") + parser.add_argument("--uart-name", default="\"serial\"", type=str, + help="UART type/name (default=serial)") + parser.add_argument("--uart-baudrate", default=None, type=int, + help="UART baudrate (default=115200)") parser.add_argument("--uart-stub", default=False, type=bool, - help="enable uart stub") - + help="enable UART stub (default=False)") + # Timer parameters + parser.add_argument("--with-timer", default=None, type=bool, + help="with Timer (default=True)") + # Controller parameters + parser.add_argument("--with-ctrl", default=None, type=bool, + help="with Controller (default=True)") def soc_core_argdict(args): r = dict()