From: Andrew Waterman <andrew@sifive.com>
Date: Thu, 25 May 2017 09:19:46 +0000 (-0700)
Subject: minNum -> minimumNumber
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba28ea06d5ca18e47d8252cb8c677d79e62b7554;p=riscv-isa-sim.git

minNum -> minimumNumber
---

diff --git a/riscv/insns/fmax_d.h b/riscv/insns/fmax_d.h
index 9c8e5b3..3d2c6e6 100644
--- a/riscv/insns/fmax_d.h
+++ b/riscv/insns/fmax_d.h
@@ -1,6 +1,8 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64_le_quiet(f64(FRS2), f64(FRS1)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
-if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+bool greater = f64_lt_quiet(f64(FRS2), f64(FRS1)) ||
+               (f64_eq(f64(FRS2), f64(FRS1)) && (f64(FRS2).v & F64_SIGN));
+WRITE_FRD(greater || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
   WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;
diff --git a/riscv/insns/fmax_s.h b/riscv/insns/fmax_s.h
index 2f570ea..33e535b 100644
--- a/riscv/insns/fmax_s.h
+++ b/riscv/insns/fmax_s.h
@@ -1,6 +1,8 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_le_quiet(f32(FRS2), f32(FRS1)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
-if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+bool greater = f32_lt_quiet(f32(FRS2), f32(FRS1)) ||
+               (f32_eq(f32(FRS2), f32(FRS1)) && (f32(FRS2).v & F32_SIGN));
+WRITE_FRD(greater || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
   WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_d.h b/riscv/insns/fmin_d.h
index cd40e15..486faa5 100644
--- a/riscv/insns/fmin_d.h
+++ b/riscv/insns/fmin_d.h
@@ -1,6 +1,8 @@
 require_extension('D');
 require_fp;
-WRITE_FRD(f64_lt_quiet(f64(FRS1), f64(FRS2)) || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
-if ((isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v)) || softfloat_exceptionFlags)
+bool less = f64_lt_quiet(f64(FRS1), f64(FRS2)) ||
+            (f64_eq(f64(FRS1), f64(FRS2)) && (f64(FRS1).v & F64_SIGN));
+WRITE_FRD(less || isNaNF64UI(f64(FRS2).v) ? FRS1 : FRS2);
+if (isNaNF64UI(f64(FRS1).v) && isNaNF64UI(f64(FRS2).v))
   WRITE_FRD(f64(defaultNaNF64UI));
 set_fp_exceptions;
diff --git a/riscv/insns/fmin_s.h b/riscv/insns/fmin_s.h
index b813f45..8099003 100644
--- a/riscv/insns/fmin_s.h
+++ b/riscv/insns/fmin_s.h
@@ -1,6 +1,8 @@
 require_extension('F');
 require_fp;
-WRITE_FRD(f32_lt_quiet(f32(FRS1), f32(FRS2)) || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
-if ((isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v)) || softfloat_exceptionFlags)
+bool less = f32_lt_quiet(f32(FRS1), f32(FRS2)) ||
+            (f32_eq(f32(FRS1), f32(FRS2)) && (f32(FRS1).v & F32_SIGN));
+WRITE_FRD(less || isNaNF32UI(f32(FRS2).v) ? FRS1 : FRS2);
+if (isNaNF32UI(f32(FRS1).v) && isNaNF32UI(f32(FRS2).v))
   WRITE_FRD(f32(defaultNaNF32UI));
 set_fp_exceptions;