From: Florent Kermarrec <florent@enjoy-digital.fr>
Date: Mon, 6 Oct 2014 10:30:06 +0000 (+0200)
Subject: mila: fixes when used without RLE
X-Git-Tag: 24jan2021_ls180~2575^2~58
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba30a01830c484f9d9f36b0388212e7c366d7807;p=litex.git

mila: fixes when used without RLE
---

diff --git a/miscope/host/drivers.py b/miscope/host/drivers.py
index ce3d7e1a..eab1d9e7 100644
--- a/miscope/host/drivers.py
+++ b/miscope/host/drivers.py
@@ -23,7 +23,7 @@ class MiIoDriver():
 		return self.miio_i.read()
 
 class MiLaDriver():
-	def __init__(self, regs, name, config_csv=None, use_rle=True):
+	def __init__(self, regs, name, config_csv=None, use_rle=False):
 		self.regs = regs
 		self.name = name
 		self.use_rle = use_rle
@@ -33,7 +33,7 @@ class MiLaDriver():
 		self.get_layout()
 		self.build_mila()
 		self.dat = Dat(self.width)
-		
+
 	def get_config(self):
 		csv_reader = csv.reader(open(self.config_csv), delimiter=',', quotechar='#')
 		for item in csv_reader:
@@ -86,14 +86,14 @@ class MiLaDriver():
 		rm.write(rising_mask)
 		fm.write(falling_mask)
 		bm.write(both_mask)
-		
+
 	def prog_sum(self, equation):
 		datas = gen_truth_table(equation)
 		for adr, dat in enumerate(datas):
 			self.mila_trigger_sum_prog_adr.write(adr)
 			self.mila_trigger_sum_prog_dat.write(dat)
 			self.mila_trigger_sum_prog_we.write(1)
-			
+
 	def config_rle(self, v):
 		self.mila_rle_enable.write(v)
 
@@ -120,8 +120,9 @@ class MiLaDriver():
 			self.dat.append(self.mila_recorder_read_dat.read())
 			empty = self.mila_recorder_read_empty.read()
 			self.mila_recorder_read_en.write(1)
-		if self.use_rle:
-			self.dat = self.dat.decode_rle()
+		if self.with_rle:
+			if self.use_rle:
+				self.dat = self.dat.decode_rle()
 		return self.dat
 
 	def export(self, export_fn=None):
diff --git a/miscope/mila.py b/miscope/mila.py
index c9f386db..5d74f317 100644
--- a/miscope/mila.py
+++ b/miscope/mila.py
@@ -36,7 +36,6 @@ class MiLa(Module, AutoCSR):
 
 		self.submodules.trigger = trigger = Trigger(width, ports)
 		self.submodules.recorder = recorder = Recorder(width, depth)
-
 		self.comb += [
 			sink.connect(trigger.sink),
 			trigger.source.connect(recorder.trig_sink)
@@ -49,7 +48,7 @@ class MiLa(Module, AutoCSR):
 				rle.source.connect(recorder.dat_sink)
 			]
 		else:
-			sink.connect(recorder.dat_sink)
+			self.comb += sink.connect(recorder.dat_sink)
 
 	def export(self, design, layout, filename):
 		ret, ns = verilog.convert(design, return_ns=True)