From: Florent Kermarrec Date: Thu, 16 Jan 2020 09:14:42 +0000 (+0100) Subject: targets: cleanup EthernetSoC X-Git-Tag: 24jan2021_ls180~740 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba366d42d093b08364de2f9fbf7972d538dcb66e;p=litex.git targets: cleanup EthernetSoC --- diff --git a/litex/boards/targets/arty.py b/litex/boards/targets/arty.py index a2a3f643..903ef594 100755 --- a/litex/boards/targets/arty.py +++ b/litex/boards/targets/arty.py @@ -84,10 +84,10 @@ class EthernetSoC(BaseSoC): # Ethernet --------------------------------------------------------------------------------- # phy - self.submodules.eth_phy = LiteEthPHYMII( + self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("eth_phy") + self.add_csr("ethphy") # mac self.submodules.ethmac = LiteEthMAC( phy = self.ethphy, @@ -115,26 +115,26 @@ class EtherboneSoC(BaseSoC): # Ethernet --------------------------------------------------------------------------------- # phy - self.submodules.eth_phy = LiteEthPHYMII( + self.submodules.ethphy = LiteEthPHYMII( clock_pads = self.platform.request("eth_clocks"), pads = self.platform.request("eth")) - self.add_csr("eth_phy") + self.add_csr("ethphy") # core - self.submodules.eth_core = LiteEthUDPIPCore( - phy = self.eth_phy, + self.submodules.ethcore = LiteEthUDPIPCore( + phy = self.ethphy, mac_address = 0x10e2d5000000, ip_address = "192.168.1.50", clk_freq = self.clk_freq) # etherbone - self.submodules.etherbone = LiteEthEtherbone(self.eth_core.udp, 1234) + self.submodules.etherbone = LiteEthEtherbone(self.ethcore.udp, 1234) self.add_wb_master(self.etherbone.wishbone.bus) # timing constraints - self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_rx.clk, 1e9/25e6) - self.platform.add_period_constraint(self.eth_phy.crg.cd_eth_tx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, - self.eth_phy.crg.cd_eth_rx.clk, - self.eth_phy.crg.cd_eth_tx.clk) + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) # Build -------------------------------------------------------------------------------------------- diff --git a/litex/boards/targets/genesys2.py b/litex/boards/targets/genesys2.py index 1d685c75..ae38c18f 100755 --- a/litex/boards/targets/genesys2.py +++ b/litex/boards/targets/genesys2.py @@ -73,16 +73,23 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kc705.py b/litex/boards/targets/kc705.py index c34b1ab0..041c4b46 100755 --- a/litex/boards/targets/kc705.py +++ b/litex/boards/targets/kc705.py @@ -75,16 +75,24 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHY(self.platform.request("eth_clocks"), - self.platform.request("eth"), clk_freq=self.clk_freq) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth"), + clk_freq = self.clk_freq) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/kcu105.py b/litex/boards/targets/kcu105.py index 9fc23c98..be25e3c2 100755 --- a/litex/boards/targets/kcu105.py +++ b/litex/boards/targets/kcu105.py @@ -110,17 +110,25 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + # Ethernet --------------------------------------------------------------------------------- + # phy self.submodules.ethphy = KU_1000BASEX(self.crg.cd_clk200.clk, - self.platform.request("sfp", 0), sys_clk_freq=self.clk_freq) + data_pads = self.platform.request("sfp", 0), + sys_clk_freq = self.clk_freq) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + self.comb += self.platform.request("sfp_tx_disable_n", 0).eq(1) + self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( @@ -128,8 +136,6 @@ class EthernetSoC(BaseSoC): self.ethphy.cd_eth_rx.clk, self.ethphy.cd_eth_tx.clk) - self.platform.add_platform_command("set_property SEVERITY {{Warning}} [get_drc_checks REQP-1753]") - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex/boards/targets/netv2.py b/litex/boards/targets/netv2.py index 90bdba02..44a64d05 100755 --- a/litex/boards/targets/netv2.py +++ b/litex/boards/targets/netv2.py @@ -23,23 +23,23 @@ from liteeth.mac import LiteEthMAC class _CRG(Module): def __init__(self, platform, sys_clk_freq): - self.clock_domains.cd_sys = ClockDomain() - self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) + self.clock_domains.cd_sys = ClockDomain() + self.clock_domains.cd_sys4x = ClockDomain(reset_less=True) self.clock_domains.cd_sys4x_dqs = ClockDomain(reset_less=True) - self.clock_domains.cd_clk200 = ClockDomain() - self.clock_domains.cd_clk100 = ClockDomain() - self.clock_domains.cd_eth = ClockDomain() + self.clock_domains.cd_clk200 = ClockDomain() + self.clock_domains.cd_clk100 = ClockDomain() + self.clock_domains.cd_eth = ClockDomain() # # # self.submodules.pll = pll = S7PLL(speedgrade=-1) pll.register_clkin(platform.request("clk50"), 50e6) - pll.create_clkout(self.cd_sys, sys_clk_freq) - pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) + pll.create_clkout(self.cd_sys, sys_clk_freq) + pll.create_clkout(self.cd_sys4x, 4*sys_clk_freq) pll.create_clkout(self.cd_sys4x_dqs, 4*sys_clk_freq, phase=90) - pll.create_clkout(self.cd_clk200, 200e6) - pll.create_clkout(self.cd_clk100, 100e6) - pll.create_clkout(self.cd_eth, 50e6) + pll.create_clkout(self.cd_clk200, 200e6) + pll.create_clkout(self.cd_clk100, 100e6) + pll.create_clkout(self.cd_eth, 50e6) self.submodules.idelayctrl = S7IDELAYCTRL(self.cd_clk200) @@ -78,24 +78,30 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/50e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/50e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex/boards/targets/nexys4ddr.py b/litex/boards/targets/nexys4ddr.py index 8999603e..b4a4494c 100755 --- a/litex/boards/targets/nexys4ddr.py +++ b/litex/boards/targets/nexys4ddr.py @@ -75,26 +75,32 @@ class EthernetSoC(BaseSoC): mem_map.update(BaseSoC.mem_map) def __init__(self, **kwargs): - BaseSoC.__init__(self, integrated_rom_size=0x10000, **kwargs) + BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/12.5e6) - self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/12.5e6) + # timing constraints + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/25e6) + self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/25e6) self.platform.add_false_path_constraints( self.crg.cd_sys.clk, self.ethphy.crg.cd_eth_rx.clk, self.ethphy.crg.cd_eth_tx.clk) - # Build -------------------------------------------------------------------------------------------- def main(): diff --git a/litex/boards/targets/nexys_video.py b/litex/boards/targets/nexys_video.py index b00c1886..9773f9ac 100755 --- a/litex/boards/targets/nexys_video.py +++ b/litex/boards/targets/nexys_video.py @@ -77,16 +77,23 @@ class EthernetSoC(BaseSoC): def __init__(self, **kwargs): BaseSoC.__init__(self, **kwargs) - self.submodules.ethphy = LiteEthPHYRGMII(self.platform.request("eth_clocks"), - self.platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHYRGMII( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") - self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, - interface="wishbone", endianness=self.cpu.endianness) + # mac + self.submodules.ethmac = LiteEthMAC( + phy = self.ethphy, + dw = 32, + interface = "wishbone", + endianness = self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) self.platform.add_false_path_constraints( diff --git a/litex/boards/targets/simple.py b/litex/boards/targets/simple.py index d04dd8d2..fa74077d 100755 --- a/litex/boards/targets/simple.py +++ b/litex/boards/targets/simple.py @@ -39,9 +39,13 @@ class EthernetSoC(BaseSoC): def __init__(self, platform, **kwargs): BaseSoC.__init__(self, platform, **kwargs) - self.submodules.ethphy = LiteEthPHY(platform.request("eth_clocks"), - platform.request("eth")) + # Ethernet --------------------------------------------------------------------------------- + # phy + self.submodules.ethphy = LiteEthPHY( + clock_pads = self.platform.request("eth_clocks"), + pads = self.platform.request("eth")) self.add_csr("ethphy") + # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness, with_preamble_crc=False) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) diff --git a/litex/boards/targets/versa_ecp5.py b/litex/boards/targets/versa_ecp5.py index fe3f0e1e..412f1544 100755 --- a/litex/boards/targets/versa_ecp5.py +++ b/litex/boards/targets/versa_ecp5.py @@ -105,19 +105,26 @@ class EthernetSoC(BaseSoC): def __init__(self, toolchain="diamond", **kwargs): BaseSoC.__init__(self, toolchain=toolchain, **kwargs) + # Ethernet --------------------------------------------------------------------------------- + # phy self.submodules.ethphy = LiteEthPHYRGMII( self.platform.request("eth_clocks"), self.platform.request("eth")) self.add_csr("ethphy") + # mac self.submodules.ethmac = LiteEthMAC(phy=self.ethphy, dw=32, interface="wishbone", endianness=self.cpu.endianness) self.add_wb_slave(self.mem_map["ethmac"], self.ethmac.bus, 0x2000) self.add_memory_region("ethmac", self.mem_map["ethmac"], 0x2000, type="io") self.add_csr("ethmac") self.add_interrupt("ethmac") - + # timing constraints self.platform.add_period_constraint(self.ethphy.crg.cd_eth_rx.clk, 1e9/125e6) self.platform.add_period_constraint(self.ethphy.crg.cd_eth_tx.clk, 1e9/125e6) + self.platform.add_false_path_constraints( + self.crg.cd_sys.clk, + self.ethphy.crg.cd_eth_rx.clk, + self.ethphy.crg.cd_eth_tx.clk) # Build --------------------------------------------------------------------------------------------