From: Tim Newsome Date: Fri, 9 Feb 2018 16:54:59 +0000 (-0800) Subject: Test resuming from a trigger. X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba39c5fc2885eb1400d6f9e13ae6c7588c1c1241;p=riscv-tests.git Test resuming from a trigger. --- diff --git a/debug/gdbserver.py b/debug/gdbserver.py index 8c500bc..f0385d5 100755 --- a/debug/gdbserver.py +++ b/debug/gdbserver.py @@ -660,12 +660,17 @@ class TriggerLoadAddressInstant(TriggerTest): self.gdb.command("b just_before_read_loop") self.gdb.c() read_loop = self.gdb.p("&read_loop") + read_again = self.gdb.p("&read_again") self.gdb.command("rwatch data") self.gdb.c() # Accept hitting the breakpoint before or after the load instruction. assertIn(self.gdb.p("$pc"), [read_loop, read_loop + 4]) assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) + self.gdb.c() + assertIn(self.gdb.p("$pc"), [read_again, read_again + 4]) + assertEqual(self.gdb.p("$a0"), self.gdb.p("&data")) + # FIXME: Triggers aren't quite working yet #class TriggerStoreAddress(TriggerTest): # def test(self): diff --git a/debug/programs/trigger.S b/debug/programs/trigger.S index 3d502dc..13f0449 100644 --- a/debug/programs/trigger.S +++ b/debug/programs/trigger.S @@ -8,16 +8,6 @@ # define LREG lw # define SREG sw # define REGBYTES 4 -#endif - -#undef MCONTROL_TYPE -#undef MCONTROL_DMODE -#if __riscv_xlen == 64 -# define MCONTROL_TYPE (0xf<<(64-4)) -# define MCONTROL_DMODE (1<<(64-5)) -#else -# define MCONTROL_TYPE (0xf<<(32-4)) -# define MCONTROL_DMODE (1<<(32-5)) #endif .global main @@ -31,7 +21,10 @@ just_before_read_loop: li t2, 16 read_loop: lw t1, 0(a0) + addi t1, t1, 1 addi t0, t0, 1 +read_again: + lw t1, 0(a0) addi a0, a0, 4 blt t0, t2, read_loop diff --git a/debug/testlib.py b/debug/testlib.py index 7727f10..3aaa542 100644 --- a/debug/testlib.py +++ b/debug/testlib.py @@ -835,6 +835,7 @@ class GdbTest(BaseTest): if not self.gdb: return self.gdb.interrupt() + self.gdb.command("disassemble") self.gdb.command("info registers all", timeout=10) def classTeardown(self):