From: Jacob Lifshay <programmerjake@gmail.com>
Date: Wed, 3 May 2023 21:28:10 +0000 (-0700)
Subject: integer mul-add is MAC not FMAC
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba43362d4d9662676cf74c6e870eabae3601ab98;p=libreriscv.git

integer mul-add is MAC not FMAC
---

diff --git a/conferences/siliconsalon2023/siliconsalon2023.tex b/conferences/siliconsalon2023/siliconsalon2023.tex
index 63cdf6f5f..09782cb13 100644
--- a/conferences/siliconsalon2023/siliconsalon2023.tex
+++ b/conferences/siliconsalon2023/siliconsalon2023.tex
@@ -139,10 +139,10 @@
 \begin{frame}[fragile]\frametitle{Vector-Scalar Multiply}
 
  \begin{itemize}
-   \item Normally in FMAC the top 64-bits is thrown away.
+   \item Normally in MAC the top 64-bits is thrown away.
    \item What if we stored those 64-bits in a 2nd register?\\
    		(64-bit carry-out)
-   \item And what if the next FMAC added that "digit" on?\\
+   \item And what if the next MAC added that "digit" on?\\
    		(64-bit carry-in)
    \item Again: a chain of these performs Vector-by-Scalar Multiply
   \end{itemize}