From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 30 Dec 2014 12:33:29 +0000 (+0100)
Subject: Fixed simlib entries for $memrd and $memwr
X-Git-Tag: yosys-0.5~176
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba43cf5807dadac970ff10afed4963d1ee329217;p=yosys.git

Fixed simlib entries for $memrd and $memwr
---

diff --git a/techlibs/common/simlib.v b/techlibs/common/simlib.v
index e241cd3ce..bacf4a17e 100644
--- a/techlibs/common/simlib.v
+++ b/techlibs/common/simlib.v
@@ -1449,6 +1449,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter TRANSPARENT = 0;
 
 input CLK;
 input [ABITS-1:0] ADDR;
@@ -1473,6 +1474,7 @@ parameter WIDTH = 8;
 
 parameter CLK_ENABLE = 0;
 parameter CLK_POLARITY = 0;
+parameter PRIORITY = 0;
 
 input CLK;
 input [WIDTH-1:0] EN;