From: Luke Kenneth Casson Leighton Date: Thu, 13 Aug 2020 17:42:12 +0000 (+0100) Subject: sync on reset in compalu X-Git-Tag: semi_working_ecp5~370 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba500c1fbb9ff4d2d7b7d16ca9d9800858acd9df;p=soc.git sync on reset in compalu --- diff --git a/src/soc/experiment/compalu_multi.py b/src/soc/experiment/compalu_multi.py index 864dc048..dbd47c8c 100644 --- a/src/soc/experiment/compalu_multi.py +++ b/src/soc/experiment/compalu_multi.py @@ -237,8 +237,8 @@ class MultiCompUnit(RegSpecALUAPI, Elaboratable): m.d.sync += rok_l.r.eq(self.alu.n.valid_o & self.busy_o) # ALU done # wr-done, back-to-start latch - m.d.comb += rst_l.s.eq(all_rd) # set when read-phase is fully done - m.d.comb += rst_l.r.eq(rst_r) # *off* on issue + m.d.sync += rst_l.s.eq(all_rd) # set when read-phase is fully done + m.d.sync += rst_l.r.eq(rst_r) # *off* on issue # opcode latch (not using go_rd_i) - inverted so that busy resets to 0 m.d.sync += opc_l.s.eq(self.issue_i) # set on issue