From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 17 Apr 2021 10:52:38 +0000 (+0100)
Subject: fix iovdd/iovss in-to-std_logic conversion
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba636eb17a7ae03b6c720f75bb137a3dd5071627;p=soc-cocotb-sim.git

fix iovdd/iovss in-to-std_logic conversion
---

diff --git a/ls180/post_pnr/vst_correct.py b/ls180/post_pnr/vst_correct.py
index 0f45466..e11ccc0 100755
--- a/ls180/post_pnr/vst_correct.py
+++ b/ls180/post_pnr/vst_correct.py
@@ -56,18 +56,18 @@ for fname in os.listdir("vst_src"):
                 if line.startswith("entity chip"):
                     found_chip = True
             else:
-                # covers in bit_vector and out bit_vector as well
-                line = line.replace("in bit", "inout std_logic")
-                line = line.replace("out bit", "inout std_logic")
+                is_power = False
+                for port in ['vss', 'vdd', 'iovss', 'iovdd']:
+                    if ' %s ' % port in line and 'in bit' in line:
+                        is_power = True
+                if not is_power:
+                    # covers in bit_vector and out bit_vector as well
+                    line = line.replace("in bit", "inout std_logic")
+                    line = line.replace("out bit", "inout std_logic")
                 done_chip = line.startswith("end chip")
             res.append(line)
         # re-join lines
         txt = '\n'.join(res)
-        # easier to just post-process-correct the iovdd std_logic
-        for port in ['vss', 'vdd', 'iovss', 'iovdd']:
-            txt = txt.replace("%-9s: inout std_logic" % port,
-                              "%-9s: in bit" % port)
-
         
     # write the file
     with open(fname, "w") as f: