From: Sandipan Das <sandipan@linux.ibm.com>
Date: Sat, 6 Feb 2021 11:42:32 +0000 (+0530)
Subject: arch-power: Use 64-bit registers and operands
X-Git-Tag: develop-gem5-snapshot~70
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba65e0108edb4c7d47af02916818f801d0ef91b2;p=gem5.git

arch-power: Use 64-bit registers and operands

This increases the width of the general-purpose registers
and some of the special purpose registers to 64 bits in
accordance with the newer versions of the Power ISA and
enables usage in both 32-bit and 64-bit execution modes.
In 32-bit mode, the use of upper word is dependent on the
instruction being executed and in some cases this may be
undefined.

Change-Id: I2a5865a66e4ceab45e42a833d425abdd6bd6bf55
Signed-off-by: Sandipan Das <sandipan@linux.ibm.com>
---

diff --git a/src/arch/power/insts/integer.hh b/src/arch/power/insts/integer.hh
index 1c9b1cc6c..d81f98d87 100644
--- a/src/arch/power/insts/integer.hh
+++ b/src/arch/power/insts/integer.hh
@@ -65,7 +65,7 @@ class IntOp : public PowerStaticInst
 
     /* Compute the CR (condition register) field using signed comparison */
     inline uint32_t
-    makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+    makeCRField(int64_t a, int64_t b, uint32_t xerSO) const
     {
         uint32_t c = xerSO;
 
@@ -76,9 +76,21 @@ class IntOp : public PowerStaticInst
         return c;
     }
 
+    inline uint32_t
+    makeCRField(int64_t a, int32_t b, uint32_t xerSO) const
+    {
+        return makeCRField(a, (int64_t)b, xerSO);
+    }
+
+    inline uint32_t
+    makeCRField(int32_t a, int32_t b, uint32_t xerSO) const
+    {
+        return makeCRField((int64_t)a, (int64_t)b, xerSO);
+    }
+
     /* Compute the CR (condition register) field using unsigned comparison */
     inline uint32_t
-    makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+    makeCRField(uint64_t a, uint64_t b, uint32_t xerSO) const
     {
         uint32_t c = xerSO;
 
@@ -89,6 +101,18 @@ class IntOp : public PowerStaticInst
         return c;
     }
 
+    inline uint32_t
+    makeCRField(uint64_t a, uint32_t b, uint32_t xerSO) const
+    {
+        return makeCRField(a, (uint64_t)b, xerSO);
+    }
+
+    inline uint32_t
+    makeCRField(uint32_t a, uint32_t b, uint32_t xerSO) const
+    {
+        return makeCRField((uint64_t)a, (uint64_t)b, xerSO);
+    }
+
     std::string generateDisassembly(
             Addr pc, const Loader::SymbolTable *symtab) const override;
 };
diff --git a/src/arch/power/isa/operands.isa b/src/arch/power/isa/operands.isa
index e77fde296..07415babd 100644
--- a/src/arch/power/isa/operands.isa
+++ b/src/arch/power/isa/operands.isa
@@ -41,10 +41,10 @@ def operand_types {{
 
 def operands {{
     # General Purpose Integer Reg Operands
-    'Ra': ('IntReg', 'uw', 'RA', 'IsInteger', 1),
-    'Rb': ('IntReg', 'uw', 'RB', 'IsInteger', 2),
-    'Rs': ('IntReg', 'uw', 'RS', 'IsInteger', 3),
-    'Rt': ('IntReg', 'uw', 'RT', 'IsInteger', 4),
+    'Ra': ('IntReg', 'ud', 'RA', 'IsInteger', 1),
+    'Rb': ('IntReg', 'ud', 'RB', 'IsInteger', 2),
+    'Rs': ('IntReg', 'ud', 'RS', 'IsInteger', 3),
+    'Rt': ('IntReg', 'ud', 'RT', 'IsInteger', 4),
 
     # General Purpose Floating Point Reg Operands
     'Fa': ('FloatReg', 'df', 'FRA', 'IsFloating', 1),
@@ -54,16 +54,16 @@ def operands {{
     'Ft': ('FloatReg', 'df', 'FRT', 'IsFloating', 5),
 
     # Memory Operand
-    'Mem': ('Mem', 'uw', None, (None, 'IsLoad', 'IsStore'), 8),
+    'Mem': ('Mem', 'ud', None, (None, 'IsLoad', 'IsStore'), 8),
 
     # Program counter and next
-    'CIA': ('PCState', 'uw', 'pc', (None, None, 'IsControl'), 9),
-    'NIA': ('PCState', 'uw', 'npc', (None, None, 'IsControl'), 9),
+    'CIA': ('PCState', 'ud', 'pc', (None, None, 'IsControl'), 9),
+    'NIA': ('PCState', 'ud', 'npc', (None, None, 'IsControl'), 9),
 
     # Control registers
     'CR': ('IntReg', 'uw', 'INTREG_CR', 'IsInteger', 9),
-    'LR': ('IntReg', 'uw', 'INTREG_LR', 'IsInteger', 9),
-    'CTR': ('IntReg', 'uw', 'INTREG_CTR', 'IsInteger', 9),
+    'LR': ('IntReg', 'ud', 'INTREG_LR', 'IsInteger', 9),
+    'CTR': ('IntReg', 'ud', 'INTREG_CTR', 'IsInteger', 9),
     'XER': ('IntReg', 'uw', 'INTREG_XER', 'IsInteger', 9),
 
     # Setting as IntReg so things are stored as an integer, not double
@@ -72,5 +72,5 @@ def operands {{
     # Registers for linked loads and stores
     'Rsv': ('IntReg', 'uw', 'INTREG_RSV', 'IsInteger', 9),
     'RsvLen': ('IntReg', 'uw', 'INTREG_RSV_LEN', 'IsInteger', 9),
-    'RsvAddr': ('IntReg', 'uw', 'INTREG_RSV_ADDR', 'IsInteger', 9),
+    'RsvAddr': ('IntReg', 'ud', 'INTREG_RSV_ADDR', 'IsInteger', 9),
 }};