From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Fri, 31 May 2019 21:05:25 +0000 (+0100)
Subject: issue from q is combinatorial so do not need set to zer0
X-Git-Tag: div_pipeline~1917
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba68e8c70ded11443bc0cbc407b7aa1993dbc641;p=soc.git

issue from q is combinatorial so do not need set to zer0
---

diff --git a/src/experiment/score6600.py b/src/experiment/score6600.py
index 4ed9acbd..12d4d625 100644
--- a/src/experiment/score6600.py
+++ b/src/experiment/score6600.py
@@ -607,26 +607,12 @@ class IssueToScoreboard(Elaboratable):
 
         with m.If(wait_issue_br | wait_issue_alu):
             # set instruction pop length to 1 if the unit accepted
-            # also tell the unit-group to stop accepting the instruction
-            # and disable the regfile
             with m.If(wait_issue_br & (sc.brissue.fn_issue_o != 0)):
                 with m.If(iq.qlen_o != 0):
                     comb += iq.n_sub_i.eq(1)
-                comb += wait_issue_br.eq(0)
-                comb += sc.brissue.insn_i.eq(0)
-                comb += sc.int_dest_i.eq(0)
-                comb += sc.int_src1_i.eq(0)
-                comb += sc.int_src2_i.eq(0)
-                comb += sc.reg_enable_i.eq(0)
             with m.If(wait_issue_alu & (sc.aluissue.fn_issue_o != 0)):
                 with m.If(iq.qlen_o != 0):
                     comb += iq.n_sub_i.eq(1)
-                comb += wait_issue_alu.eq(0)
-                comb += sc.aluissue.insn_i.eq(0)
-                comb += sc.int_dest_i.eq(0)
-                comb += sc.int_src1_i.eq(0)
-                comb += sc.int_src2_i.eq(0)
-                comb += sc.reg_enable_i.eq(0)
 
         # see if some instruction(s) are here.  note that this is
         # "inspecting" the in-place queue.  note also that on the