From: Tobias Platen <tplaten@posteo.de>
Date: Sun, 7 Aug 2022 17:56:34 +0000 (+0200)
Subject: comment out reset signal for iverilog simulation
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba7d6761286ec2ea6e47b89de5dc0599bf7a6f34;p=ls2.git

comment out reset signal for iverilog simulation
---

diff --git a/src/simsoctb.v b/src/simsoctb.v
index 64fb39a..da3b2e0 100644
--- a/src/simsoctb.v
+++ b/src/simsoctb.v
@@ -90,7 +90,7 @@ module simsoctb;
   //defparam ram_chip.
   
   top simsoctop (
-    .ddr3_0__rst__io(dram_rst),
+     //FIXME .ddr3_0__rst__io(dram_rst),
     .ddr3_0__dq__io(dram_dq),
     .ddr3_0__dqs__p(dram_dqs),
     .ddr3_0__clk__p(dram_ck),