From: lkcl <lkcl@web>
Date: Tue, 25 Apr 2023 14:15:35 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba8be6837946541c91738956e79f6b6d52e3c2c0;p=libreriscv.git

---

diff --git a/openpower/sv/cr_int_predication.mdwn b/openpower/sv/cr_int_predication.mdwn
index ed9474448..2f5752c6f 100644
--- a/openpower/sv/cr_int_predication.mdwn
+++ b/openpower/sv/cr_int_predication.mdwn
@@ -97,13 +97,14 @@ OPF ISA WG):
 |19 |BT   |M |fmsk |BFA  | 1 1 |0 fmap |00011  |0 |crweirder |
 |19 |BF //|M |fmsk |BFA  | 1 1 |0 fmap |00011  |1 |mcrfm     |
 
-**crrweird**
+## crrweird
 
-fmap is encoded in XO and is 4 bits
+CW2-Form
 
-```
-    crrweird: RT,BFA,M,fmsk,fmap
+* crrweird: RT,BFA,M,fmsk,fmap
+* crrweird.: RT,BFA,M,fmsk,fmap
 
+```
     creg = CR{BFA}
     n0 = fmsk[0] & (fmap[0] == creg[0])
     n1 = fmsk[1] & (fmap[1] == creg[1])
@@ -124,6 +125,12 @@ Also as noted below, element-width override bits normally used
 on the source is instead used to allow multiple results to be packed
 sequentially into the destination. *Destination elwidth overrides still apply*.
 
+Special registers altered:
+
+```
+    CR0        (Rc=1)
+```
+
 **mfcrrweird**
 
 fmap is encoded in XO and is 4 bits