From: lkcl <lkcl@web>
Date: Sun, 30 Apr 2023 23:18:45 +0000 (+0100)
Subject: (no commit message)
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba94a2bdcf5d61df7578730932357822dc2b494f;p=libreriscv.git

---

diff --git a/openpower/sv/twin_butterfly.mdwn b/openpower/sv/twin_butterfly.mdwn
index 534d62194..e06a2899e 100644
--- a/openpower/sv/twin_butterfly.mdwn
+++ b/openpower/sv/twin_butterfly.mdwn
@@ -90,7 +90,6 @@ A-Form
 ```
     |0     |6     |11      |16     |21      |26    |31 |
     | PO   |  RT  |   RA   |   RB  |   SH   |   XO |Rc |
-
 ```
 
 * maddsubrs  RT,RA,SH,RB
@@ -146,7 +145,7 @@ Special Registers Altered:
 
 \newpage{}
 
-# Twin Butterfly Floating-Point DCT Instruction(s)
+# Twin Butterfly Floating-Point DCT and FFT Instruction(s)
 
 **Add the following to Book I Section 4.6.6.3**
 
@@ -242,7 +241,7 @@ stored in FRS.
 
 Using the exact same values of FRT, FRT and FRB as used to create
 FRS, the floating-point operand in register FRT is multiplied by the
-floating-point operand in register FRA. The float- ing-point operand
+floating-point operand in register FRA. The floating-point operand
 in register FRB is subtracted from this intermediate result, and the
 intermediate stored in FRT.
 
@@ -262,7 +261,6 @@ For SVP64 if `FRT` is a Vector, `FRS` begins immediately after the
 Vector `FRT` where the length of `FRT` is set by `SVSTATE.MAXVL`
 (Max Vector Length).
 
-
 Special Registers Altered:
 
 ```
@@ -270,6 +268,7 @@ Special Registers Altered:
     FX OX UX XX
     VXSNAN VXISI VXIMZ
 ```
+
 ## Floating-Point Twin Multiply-Add DCT
 
 X-Form
@@ -389,12 +388,16 @@ Special Registers Altered:
 ```
 
 
-## [DRAFT] Floating-Point Add FFT/DCT [Single]
+## Floating-Point Add FFT/DCT [Single]
 
 A-Form
 
+```
+    |0     |6     |11      |16     |21      |26    |31 |
+    | PO   | FRT  |  FRA   |  FRB  |     /  |   XO |Rc |
+```
+
 * ffadds FRT,FRA,FRB (Rc=0)
-* ffadds. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -409,15 +412,18 @@ Special Registers Altered:
     FPRF FR FI
     FX OX UX XX
     VXSNAN VXISI
-    CR1          (if Rc=1)
 ```
 
-## [DRAFT] Floating-Point Add FFT/DCT [Double]
+## Floating-Point Add FFT/DCT [Double]
 
 A-Form
 
+```
+    |0     |6     |11      |16     |21      |26    |31 |
+    | PO   | FRT  |  FRA   |  FRB  |     /  |   XO |Rc |
+```
+
 * ffadd FRT,FRA,FRB (Rc=0)
-* ffadd. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -432,15 +438,18 @@ Special Registers Altered:
     FPRF FR FI
     FX OX UX XX
     VXSNAN VXISI
-    CR1          (if Rc=1)
 ```
 
-## [DRAFT] Floating-Point Subtract FFT/DCT [Single]
+## Floating-Point Subtract FFT/DCT [Single]
 
 A-Form
 
+```
+    |0     |6     |11      |16     |21      |26    |31 |
+    | PO   | FRT  |  FRA   |  FRB  |     /  |   XO |Rc |
+```
+
 * ffsubs FRT,FRA,FRB (Rc=0)
-* ffsubs. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -455,15 +464,18 @@ Special Registers Altered:
     FPRF FR FI
     FX OX UX XX
     VXSNAN VXISI
-    CR1          (if Rc=1)
 ```
 
-## [DRAFT] Floating-Point Subtract FFT/DCT [Double]
+## Floating-Point Subtract FFT/DCT [Double]
 
 A-Form
 
+```
+    |0     |6     |11      |16     |21      |26    |31 |
+    | PO   | FRT  |  FRA   |  FRB  |     /  |   XO |Rc |
+```
+
 * ffsub FRT,FRA,FRB (Rc=0)
-* ffsub. FRT,FRA,FRB (Rc=1)
 
 Pseudo-code:
 
@@ -478,5 +490,4 @@ Special Registers Altered:
     FPRF FR FI
     FX OX UX XX
     VXSNAN VXISI
-    CR1          (if Rc=1)
 ```