From: Luke Kenneth Casson Leighton <lkcl@lkcl.net>
Date: Sat, 8 Oct 2022 13:37:33 +0000 (+0100)
Subject: add rfscv to major_19.csv, add test_pysvp64dis.py unit test
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=ba99459eb3febc23a9b0e743c9e1dece2979f735;p=openpower-isa.git

add rfscv to major_19.csv, add test_pysvp64dis.py unit test
---

diff --git a/openpower/isatables/minor_19.csv b/openpower/isatables/minor_19.csv
index d6dbbb55..0518de65 100644
--- a/openpower/isatables/minor_19.csv
+++ b/openpower/isatables/minor_19.csv
@@ -14,6 +14,7 @@ opcode,unit,internal op,in1,in2,in3,out,CR in,CR out,inv A,inv out,cry in,cry ou
 0000010000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bclr,XL,
 1000110000,BRANCH,OP_BCREG,SPR,SPR,NONE,SPR,BI,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,1,0,bctar,XL,
 0010010110,ALU,OP_ISYNC,NONE,NONE,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,isync,XL,
+0001010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,rfscv,XL,
 0000010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,rfid,XL,
 0100010010,TRAP,OP_RFID,SPR,SPR,NONE,NONE,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,0,hrfid,XL,
 -----00010,ALU,OP_ADD,CIA,CONST_DXHI4,NONE,RT,NONE,NONE,0,0,ZERO,0,NONE,0,0,0,0,0,0,NONE,0,1,addpcis,DX,
diff --git a/src/openpower/sv/trans/test_pysvp64dis.py b/src/openpower/sv/trans/test_pysvp64dis.py
index a5dcbe04..808b3b50 100644
--- a/src/openpower/sv/trans/test_pysvp64dis.py
+++ b/src/openpower/sv/trans/test_pysvp64dis.py
@@ -377,6 +377,13 @@ class SVSTATETestCase(unittest.TestCase):
                         ]
         self._do_tst(expected)
 
+    def test_28_rfid(self):
+        expected = [
+                    "rfid",
+                    "rfscv",
+                        ]
+        self._do_tst(expected)
+
 
 if __name__ == "__main__":
     unittest.main()