From: Kevin Lim Date: Fri, 16 Jun 2006 21:08:47 +0000 (-0400) Subject: Two updates that got combined into one ChangeSet accidentally. They're both pretty... X-Git-Tag: m5_2.0_beta1~36^2~59^2~5^2~3 X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=baba18ab9214d1fe2236cd932c3bfca5ddfb06d6;p=gem5.git Two updates that got combined into one ChangeSet accidentally. They're both pretty simple so they shouldn't cause any trouble. First: Rename FullCPU and its variants in the o3 directory to O3CPU to differentiate from the old model, and also to specify it's an out of order model. Second: Include build options for selecting the Checker to be used. These options make sure if the Checker is being used there is a CPU that supports it also being compiled. SConstruct: Add in option USE_CHECKER to allow for not compiling in checker code. The checker is enabled through this option instead of through the CPU_MODELS list. However it's still necessary to treat the Checker like a CPU model, so it is appended onto the CPU_MODELS list if enabled. configs/test/test.py: Name change for DetailedCPU to DetailedO3CPU. Also include option for max tick. src/base/traceflags.py: Add in O3CPU trace flag. src/cpu/SConscript: Rename AlphaFullCPU to AlphaO3CPU. Only include checker sources if they're necessary. Also add a list of CPUs that support the Checker, and only allow the Checker to be compiled in if one of those CPUs are also being included. src/cpu/base_dyn_inst.cc: src/cpu/base_dyn_inst.hh: Rename typedef to ImplCPU instead of FullCPU, to differentiate from the old FullCPU. src/cpu/cpu_models.py: src/cpu/o3/alpha_cpu.cc: src/cpu/o3/alpha_cpu.hh: src/cpu/o3/alpha_cpu_builder.cc: src/cpu/o3/alpha_cpu_impl.hh: Rename AlphaFullCPU to AlphaO3CPU to differentiate from old FullCPU model. src/cpu/o3/alpha_dyn_inst.hh: src/cpu/o3/alpha_dyn_inst_impl.hh: src/cpu/o3/alpha_impl.hh: src/cpu/o3/alpha_params.hh: src/cpu/o3/commit.hh: src/cpu/o3/cpu.hh: src/cpu/o3/decode.hh: src/cpu/o3/decode_impl.hh: src/cpu/o3/fetch.hh: src/cpu/o3/iew.hh: src/cpu/o3/iew_impl.hh: src/cpu/o3/inst_queue.hh: src/cpu/o3/lsq.hh: src/cpu/o3/lsq_impl.hh: src/cpu/o3/lsq_unit.hh: src/cpu/o3/regfile.hh: src/cpu/o3/rename.hh: src/cpu/o3/rename_impl.hh: src/cpu/o3/rob.hh: src/cpu/o3/rob_impl.hh: src/cpu/o3/thread_state.hh: src/python/m5/objects/AlphaO3CPU.py: Rename FullCPU to O3CPU to differentiate from old FullCPU model. src/cpu/o3/commit_impl.hh: src/cpu/o3/cpu.cc: src/cpu/o3/fetch_impl.hh: src/cpu/o3/lsq_unit_impl.hh: Rename FullCPU to O3CPU to differentiate from old FullCPU model. Also #ifdef the checker code so it doesn't need to be included if it's not selected. --HG-- rename : src/cpu/checker/o3_cpu_builder.cc => src/cpu/checker/o3_builder.cc rename : src/cpu/checker/cpu_builder.cc => src/cpu/checker/ozone_builder.cc rename : src/python/m5/objects/AlphaFullCPU.py => src/python/m5/objects/AlphaO3CPU.py extra : convert_revision : 86619baf257b8b7c8955efd447eba56e0d7acd6a --- diff --git a/SConstruct b/SConstruct index 0cf15b1f9..c9ba13679 100644 --- a/SConstruct +++ b/SConstruct @@ -260,8 +260,8 @@ env['ALL_ISA_LIST'] = ['alpha', 'sparc', 'mips'] # Define the universe of supported CPU models env['ALL_CPU_LIST'] = ['AtomicSimpleCPU', 'TimingSimpleCPU', - 'FullCPU', 'AlphaFullCPU', - 'OzoneSimpleCPU', 'OzoneCPU', 'CheckerCPU'] + 'FullCPU', 'AlphaO3CPU', + 'OzoneSimpleCPU', 'OzoneCPU'] # Sticky options get saved in the options file so they persist from # one invocation to the next (unless overridden, in which case the new @@ -289,6 +289,7 @@ sticky_opts.AddOptions( False), BoolOption('USE_MYSQL', 'Use MySQL for stats output', have_mysql), BoolOption('USE_FENV', 'Use IEEE mode control', have_fenv), + BoolOption('USE_CHECKER', 'Use checker for detailed CPU models', False), ('CC', 'C compiler', os.environ.get('CC', env['CC'])), ('CXX', 'C++ compiler', os.environ.get('CXX', env['CXX'])), BoolOption('BATCH', 'Use batch pool for build and tests', False), @@ -303,7 +304,8 @@ nonsticky_opts.AddOptions( # These options get exported to #defines in config/*.hh (see m5/SConscript). env.ExportOptions = ['FULL_SYSTEM', 'ALPHA_TLASER', 'USE_FENV', \ - 'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP'] + 'USE_MYSQL', 'NO_FAST_ALLOC', 'SS_COMPATIBLE_FP', \ + 'USE_CHECKER'] # Define a handy 'no-op' action def no_action(target, source, env): @@ -470,6 +472,10 @@ for build_path in build_paths: env.ParseConfig(mysql_config_libs) env.ParseConfig(mysql_config_include) + # Check if the Checker is being used. If so append it to env['CPU_MODELS'] + if env['USE_CHECKER']: + env['CPU_MODELS'].append('CheckerCPU') + # Save sticky option settings back to current options file sticky_opts.Save(current_opts_file, env) diff --git a/configs/test/test.py b/configs/test/test.py index 2ece9e675..05fdb7786 100644 --- a/configs/test/test.py +++ b/configs/test/test.py @@ -14,6 +14,7 @@ parser = optparse.OptionParser(option_list=m5.standardOptions) parser.add_option("-c", "--cmd", default="hello") parser.add_option("-t", "--timing", action="store_true") parser.add_option("-f", "--full", action="store_true") +parser.add_option("-m", "--maxtick", type="int") (options, args) = parser.parse_args() @@ -34,7 +35,7 @@ mem = PhysicalMemory() if options.timing: cpu = TimingSimpleCPU() elif options.full: - cpu = DetailedCPU() + cpu = DetailedO3CPU() else: cpu = AtomicSimpleCPU() cpu.workload = process @@ -48,7 +49,10 @@ root = Root(system = system) m5.instantiate(root) # simulate until program terminates -exit_event = m5.simulate() +if options.maxtick: + exit_event = m5.simulate(options.maxtick) +else: + exit_event = m5.simulate() print 'Exiting @', m5.curTick(), 'because', exit_event.getCause() diff --git a/src/base/traceflags.py b/src/base/traceflags.py index 7ff68bcaf..c4dcb695b 100644 --- a/src/base/traceflags.py +++ b/src/base/traceflags.py @@ -115,6 +115,7 @@ baseFlags = [ 'MSHR', 'Mbox', 'MemDepUnit', + 'O3CPU', 'OzoneCPU', 'FE', 'IBE', diff --git a/src/cpu/SConscript b/src/cpu/SConscript index 34bad132c..608625ed4 100644 --- a/src/cpu/SConscript +++ b/src/cpu/SConscript @@ -92,6 +92,10 @@ env.Command('static_inst_exec_sigs.hh', models_db, Action(gen_cpu_exec_signatures, gen_sigs_string, varlist = ['CPU_MODELS'])) +# List of suppported CPUs by the Checker. Errors out if USE_CHECKER=True +# and one of these are not being used. +CheckerSupportedCPUList = ['AlphaO3CPU', 'OzoneCPU'] + ################################################################# # # Include CPU-model-specific files based on set of models @@ -116,7 +120,7 @@ if need_simple_base: if 'FastCPU' in env['CPU_MODELS']: sources += Split('fast/cpu.cc') -if 'AlphaFullCPU' in env['CPU_MODELS']: +if 'AlphaO3CPU' in env['CPU_MODELS']: sources += Split(''' base_dyn_inst.cc o3/2bit_local_pred.cc @@ -144,6 +148,8 @@ if 'AlphaFullCPU' in env['CPU_MODELS']: o3/store_set.cc o3/tournament_pred.cc ''') + if 'CheckerCPU' in env['CPU_MODELS']: + sources += Split('checker/o3_builder.cc') if 'OzoneSimpleCPU' in env['CPU_MODELS']: sources += Split(''' @@ -155,6 +161,8 @@ if 'OzoneSimpleCPU' in env['CPU_MODELS']: ozone/inst_queue.cc ozone/rename_table.cc ''') + if 'CheckerCPU' in env['CPU_MODELS']: + sources += Split('checker/ozone_builder.cc') if 'OzoneCPU' in env['CPU_MODELS']: sources += Split(''' @@ -164,10 +172,17 @@ if 'OzoneCPU' in env['CPU_MODELS']: ''') if 'CheckerCPU' in env['CPU_MODELS']: - sources += Split(''' - checker/cpu.cc - checker/o3_cpu_builder.cc - ''') + sources += Split('checker/cpu.cc') + checker_supports = False + for i in CheckerSupportedCPUList: + if i in env['CPU_MODELS']: + checker_supports = True + if not checker_supports: + print "Checker only supports CPU models %s, please " \ + "set USE_CHECKER=False or use one of those CPU models" \ + % CheckerSupportedCPUList + Exit(1) + # FullCPU sources are included from m5/SConscript since they're not # below this point in the file hierarchy. diff --git a/src/cpu/base_dyn_inst.cc b/src/cpu/base_dyn_inst.cc index 4bcd59848..5e2a6392a 100644 --- a/src/cpu/base_dyn_inst.cc +++ b/src/cpu/base_dyn_inst.cc @@ -71,8 +71,8 @@ my_hash_t thishash; template BaseDynInst::BaseDynInst(ExtMachInst machInst, Addr inst_PC, Addr pred_PC, InstSeqNum seq_num, - FullCPU *cpu) - : staticInst(machInst), traceData(NULL), cpu(cpu)/*, xc(cpu->xcBase())*/ + ImplCPU *cpu) + : staticInst(machInst), traceData(NULL), cpu(cpu) { seqNum = seq_num; diff --git a/src/cpu/base_dyn_inst.hh b/src/cpu/base_dyn_inst.hh index f188e661c..9cc61f74c 100644 --- a/src/cpu/base_dyn_inst.hh +++ b/src/cpu/base_dyn_inst.hh @@ -59,8 +59,8 @@ class BaseDynInst : public FastAlloc, public RefCounted { public: // Typedef for the CPU. - typedef typename Impl::FullCPU FullCPU; - typedef typename FullCPU::ImplState ImplState; + typedef typename Impl::CPUType ImplCPU; + typedef typename ImplCPU::ImplState ImplState; // Binary machine instruction type. typedef TheISA::MachInst MachInst; @@ -165,8 +165,8 @@ class BaseDynInst : public FastAlloc, public RefCounted /** How many source registers are ready. */ unsigned readyRegs; - /** Pointer to the FullCPU object. */ - FullCPU *cpu; + /** Pointer to the Impl's CPU object. */ + ImplCPU *cpu; /** Pointer to the thread state. */ ImplState *thread; @@ -239,7 +239,7 @@ class BaseDynInst : public FastAlloc, public RefCounted * @param cpu Pointer to the instruction's CPU. */ BaseDynInst(ExtMachInst inst, Addr PC, Addr pred_PC, InstSeqNum seq_num, - FullCPU *cpu); + ImplCPU *cpu); /** BaseDynInst constructor given a StaticInst pointer. * @param _staticInst The StaticInst for this BaseDynInst. diff --git a/src/cpu/checker/cpu_builder.cc b/src/cpu/checker/cpu_builder.cc deleted file mode 100644 index 3c43ab503..000000000 --- a/src/cpu/checker/cpu_builder.cc +++ /dev/null @@ -1,162 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include - -#include "cpu/checker/cpu.hh" -#include "cpu/inst_seq.hh" -#include "cpu/ozone/dyn_inst.hh" -#include "cpu/ozone/ozone_impl.hh" -#include "mem/base_mem.hh" -#include "sim/builder.hh" -#include "sim/process.hh" -#include "sim/sim_object.hh" - -/** - * Specific non-templated derived class used for SimObject configuration. - */ -class OzoneChecker : public Checker > > -{ - public: - OzoneChecker(Params *p) - : Checker > >(p) - { } -}; - -//////////////////////////////////////////////////////////////////////// -// -// CheckerCPU Simulation Object -// -BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) - - Param max_insts_any_thread; - Param max_insts_all_threads; - Param max_loads_any_thread; - Param max_loads_all_threads; - -#if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; - SimObjectParam mem; - SimObjectParam system; - Param cpu_id; - Param profile; -#else - SimObjectParam workload; -#endif // FULL_SYSTEM - Param clock; - SimObjectParam icache; - SimObjectParam dcache; - - Param defer_registration; - Param exitOnError; - Param warnOnlyOnLoadError; - Param function_trace; - Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) - -BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) - - INIT_PARAM(max_insts_any_thread, - "terminate when any thread reaches this inst count"), - INIT_PARAM(max_insts_all_threads, - "terminate when all threads have reached this inst count"), - INIT_PARAM(max_loads_any_thread, - "terminate when any thread reaches this load count"), - INIT_PARAM(max_loads_all_threads, - "terminate when all threads have reached this load count"), - -#if FULL_SYSTEM - INIT_PARAM(itb, "Instruction TLB"), - INIT_PARAM(dtb, "Data TLB"), - INIT_PARAM(mem, "memory"), - INIT_PARAM(system, "system object"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM(profile, ""), -#else - INIT_PARAM(workload, "processes to run"), -#endif // FULL_SYSTEM - - INIT_PARAM(clock, "clock speed"), - INIT_PARAM(icache, "L1 instruction cache object"), - INIT_PARAM(dcache, "L1 data cache object"), - - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - INIT_PARAM(exitOnError, "exit on error"), - INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load " - "result errors", false), - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(OzoneChecker) - - -CREATE_SIM_OBJECT(OzoneChecker) -{ - OzoneChecker::Params *params = new OzoneChecker::Params(); - params->name = getInstanceName(); - params->numberOfThreads = 1; - params->max_insts_any_thread = 0; - params->max_insts_all_threads = 0; - params->max_loads_any_thread = 0; - params->max_loads_all_threads = 0; - params->exitOnError = exitOnError; - params->warnOnlyOnLoadError = warnOnlyOnLoadError; - params->deferRegistration = defer_registration; - params->functionTrace = function_trace; - params->functionTraceStart = function_trace_start; - params->clock = clock; - // Hack to touch all parameters. Consider not deriving Checker - // from BaseCPU..it's not really a CPU in the end. - Counter temp; - temp = max_insts_any_thread; - temp = max_insts_all_threads; - temp = max_loads_any_thread; - temp = max_loads_all_threads; - BaseMem *cache = icache; - cache = dcache; - -#if FULL_SYSTEM - params->itb = itb; - params->dtb = dtb; - params->mem = mem; - params->system = system; - params->cpu_id = cpu_id; - params->profile = profile; -#else - params->process = workload; -#endif - - OzoneChecker *cpu = new OzoneChecker(params); - return cpu; -} - -REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker) diff --git a/src/cpu/checker/o3_builder.cc b/src/cpu/checker/o3_builder.cc new file mode 100644 index 000000000..534a5e28c --- /dev/null +++ b/src/cpu/checker/o3_builder.cc @@ -0,0 +1,154 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include + +#include "cpu/checker/cpu.hh" +#include "cpu/inst_seq.hh" +#include "cpu/o3/alpha_dyn_inst.hh" +#include "cpu/o3/alpha_impl.hh" +#include "sim/builder.hh" +#include "sim/process.hh" +#include "sim/sim_object.hh" + +class MemObject; + +/** + * Specific non-templated derived class used for SimObject configuration. + */ +class O3Checker : public Checker > > +{ + public: + O3Checker(Params *p) + : Checker > >(p) + { } +}; + +//////////////////////////////////////////////////////////////////////// +// +// CheckerCPU Simulation Object +// +BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) + + Param max_insts_any_thread; + Param max_insts_all_threads; + Param max_loads_any_thread; + Param max_loads_all_threads; + +#if FULL_SYSTEM + SimObjectParam itb; + SimObjectParam dtb; + SimObjectParam system; + Param cpu_id; + Param profile; +#else + SimObjectParam workload; +#endif // FULL_SYSTEM + Param clock; + + Param defer_registration; + Param exitOnError; + Param warnOnlyOnLoadError; + Param function_trace; + Param function_trace_start; + +END_DECLARE_SIM_OBJECT_PARAMS(O3Checker) + +BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) + + INIT_PARAM(max_insts_any_thread, + "terminate when any thread reaches this inst count"), + INIT_PARAM(max_insts_all_threads, + "terminate when all threads have reached this inst count"), + INIT_PARAM(max_loads_any_thread, + "terminate when any thread reaches this load count"), + INIT_PARAM(max_loads_all_threads, + "terminate when all threads have reached this load count"), + +#if FULL_SYSTEM + INIT_PARAM(itb, "Instruction TLB"), + INIT_PARAM(dtb, "Data TLB"), + INIT_PARAM(system, "system object"), + INIT_PARAM(cpu_id, "processor ID"), + INIT_PARAM(profile, ""), +#else + INIT_PARAM(workload, "processes to run"), +#endif // FULL_SYSTEM + + INIT_PARAM(clock, "clock speed"), + + INIT_PARAM(defer_registration, "defer system registration (for sampling)"), + INIT_PARAM(exitOnError, "exit on error"), + INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load " + "result errors", false), + INIT_PARAM(function_trace, "Enable function trace"), + INIT_PARAM(function_trace_start, "Cycle to start function trace") + +END_INIT_SIM_OBJECT_PARAMS(O3Checker) + + +CREATE_SIM_OBJECT(O3Checker) +{ + O3Checker::Params *params = new O3Checker::Params(); + params->name = getInstanceName(); + params->numberOfThreads = 1; + params->max_insts_any_thread = 0; + params->max_insts_all_threads = 0; + params->max_loads_any_thread = 0; + params->max_loads_all_threads = 0; + params->exitOnError = exitOnError; + params->warnOnlyOnLoadError = warnOnlyOnLoadError; + params->deferRegistration = defer_registration; + params->functionTrace = function_trace; + params->functionTraceStart = function_trace_start; + params->clock = clock; + // Hack to touch all parameters. Consider not deriving Checker + // from BaseCPU..it's not really a CPU in the end. + Counter temp; + temp = max_insts_any_thread; + temp = max_insts_all_threads; + temp = max_loads_any_thread; + temp = max_loads_all_threads; + +#if FULL_SYSTEM + params->itb = itb; + params->dtb = dtb; + params->system = system; + params->cpu_id = cpu_id; + params->profile = profile; +#else + params->process = workload; +#endif + + O3Checker *cpu = new O3Checker(params); + return cpu; +} + +REGISTER_SIM_OBJECT("O3Checker", O3Checker) diff --git a/src/cpu/checker/o3_cpu_builder.cc b/src/cpu/checker/o3_cpu_builder.cc deleted file mode 100644 index 534a5e28c..000000000 --- a/src/cpu/checker/o3_cpu_builder.cc +++ /dev/null @@ -1,154 +0,0 @@ -/* - * Copyright (c) 2006 The Regents of The University of Michigan - * All rights reserved. - * - * Redistribution and use in source and binary forms, with or without - * modification, are permitted provided that the following conditions are - * met: redistributions of source code must retain the above copyright - * notice, this list of conditions and the following disclaimer; - * redistributions in binary form must reproduce the above copyright - * notice, this list of conditions and the following disclaimer in the - * documentation and/or other materials provided with the distribution; - * neither the name of the copyright holders nor the names of its - * contributors may be used to endorse or promote products derived from - * this software without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS - * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT - * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR - * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT - * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, - * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT - * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, - * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY - * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - * Authors: Kevin Lim - */ - -#include - -#include "cpu/checker/cpu.hh" -#include "cpu/inst_seq.hh" -#include "cpu/o3/alpha_dyn_inst.hh" -#include "cpu/o3/alpha_impl.hh" -#include "sim/builder.hh" -#include "sim/process.hh" -#include "sim/sim_object.hh" - -class MemObject; - -/** - * Specific non-templated derived class used for SimObject configuration. - */ -class O3Checker : public Checker > > -{ - public: - O3Checker(Params *p) - : Checker > >(p) - { } -}; - -//////////////////////////////////////////////////////////////////////// -// -// CheckerCPU Simulation Object -// -BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker) - - Param max_insts_any_thread; - Param max_insts_all_threads; - Param max_loads_any_thread; - Param max_loads_all_threads; - -#if FULL_SYSTEM - SimObjectParam itb; - SimObjectParam dtb; - SimObjectParam system; - Param cpu_id; - Param profile; -#else - SimObjectParam workload; -#endif // FULL_SYSTEM - Param clock; - - Param defer_registration; - Param exitOnError; - Param warnOnlyOnLoadError; - Param function_trace; - Param function_trace_start; - -END_DECLARE_SIM_OBJECT_PARAMS(O3Checker) - -BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker) - - INIT_PARAM(max_insts_any_thread, - "terminate when any thread reaches this inst count"), - INIT_PARAM(max_insts_all_threads, - "terminate when all threads have reached this inst count"), - INIT_PARAM(max_loads_any_thread, - "terminate when any thread reaches this load count"), - INIT_PARAM(max_loads_all_threads, - "terminate when all threads have reached this load count"), - -#if FULL_SYSTEM - INIT_PARAM(itb, "Instruction TLB"), - INIT_PARAM(dtb, "Data TLB"), - INIT_PARAM(system, "system object"), - INIT_PARAM(cpu_id, "processor ID"), - INIT_PARAM(profile, ""), -#else - INIT_PARAM(workload, "processes to run"), -#endif // FULL_SYSTEM - - INIT_PARAM(clock, "clock speed"), - - INIT_PARAM(defer_registration, "defer system registration (for sampling)"), - INIT_PARAM(exitOnError, "exit on error"), - INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load " - "result errors", false), - INIT_PARAM(function_trace, "Enable function trace"), - INIT_PARAM(function_trace_start, "Cycle to start function trace") - -END_INIT_SIM_OBJECT_PARAMS(O3Checker) - - -CREATE_SIM_OBJECT(O3Checker) -{ - O3Checker::Params *params = new O3Checker::Params(); - params->name = getInstanceName(); - params->numberOfThreads = 1; - params->max_insts_any_thread = 0; - params->max_insts_all_threads = 0; - params->max_loads_any_thread = 0; - params->max_loads_all_threads = 0; - params->exitOnError = exitOnError; - params->warnOnlyOnLoadError = warnOnlyOnLoadError; - params->deferRegistration = defer_registration; - params->functionTrace = function_trace; - params->functionTraceStart = function_trace_start; - params->clock = clock; - // Hack to touch all parameters. Consider not deriving Checker - // from BaseCPU..it's not really a CPU in the end. - Counter temp; - temp = max_insts_any_thread; - temp = max_insts_all_threads; - temp = max_loads_any_thread; - temp = max_loads_all_threads; - -#if FULL_SYSTEM - params->itb = itb; - params->dtb = dtb; - params->system = system; - params->cpu_id = cpu_id; - params->profile = profile; -#else - params->process = workload; -#endif - - O3Checker *cpu = new O3Checker(params); - return cpu; -} - -REGISTER_SIM_OBJECT("O3Checker", O3Checker) diff --git a/src/cpu/checker/ozone_builder.cc b/src/cpu/checker/ozone_builder.cc new file mode 100644 index 000000000..3c43ab503 --- /dev/null +++ b/src/cpu/checker/ozone_builder.cc @@ -0,0 +1,162 @@ +/* + * Copyright (c) 2006 The Regents of The University of Michigan + * All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer; + * redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution; + * neither the name of the copyright holders nor the names of its + * contributors may be used to endorse or promote products derived from + * this software without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR + * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT + * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, + * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT + * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, + * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY + * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT + * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + * Authors: Kevin Lim + */ + +#include + +#include "cpu/checker/cpu.hh" +#include "cpu/inst_seq.hh" +#include "cpu/ozone/dyn_inst.hh" +#include "cpu/ozone/ozone_impl.hh" +#include "mem/base_mem.hh" +#include "sim/builder.hh" +#include "sim/process.hh" +#include "sim/sim_object.hh" + +/** + * Specific non-templated derived class used for SimObject configuration. + */ +class OzoneChecker : public Checker > > +{ + public: + OzoneChecker(Params *p) + : Checker > >(p) + { } +}; + +//////////////////////////////////////////////////////////////////////// +// +// CheckerCPU Simulation Object +// +BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) + + Param max_insts_any_thread; + Param max_insts_all_threads; + Param max_loads_any_thread; + Param max_loads_all_threads; + +#if FULL_SYSTEM + SimObjectParam itb; + SimObjectParam dtb; + SimObjectParam mem; + SimObjectParam system; + Param cpu_id; + Param profile; +#else + SimObjectParam workload; +#endif // FULL_SYSTEM + Param clock; + SimObjectParam icache; + SimObjectParam dcache; + + Param defer_registration; + Param exitOnError; + Param warnOnlyOnLoadError; + Param function_trace; + Param function_trace_start; + +END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker) + +BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker) + + INIT_PARAM(max_insts_any_thread, + "terminate when any thread reaches this inst count"), + INIT_PARAM(max_insts_all_threads, + "terminate when all threads have reached this inst count"), + INIT_PARAM(max_loads_any_thread, + "terminate when any thread reaches this load count"), + INIT_PARAM(max_loads_all_threads, + "terminate when all threads have reached this load count"), + +#if FULL_SYSTEM + INIT_PARAM(itb, "Instruction TLB"), + INIT_PARAM(dtb, "Data TLB"), + INIT_PARAM(mem, "memory"), + INIT_PARAM(system, "system object"), + INIT_PARAM(cpu_id, "processor ID"), + INIT_PARAM(profile, ""), +#else + INIT_PARAM(workload, "processes to run"), +#endif // FULL_SYSTEM + + INIT_PARAM(clock, "clock speed"), + INIT_PARAM(icache, "L1 instruction cache object"), + INIT_PARAM(dcache, "L1 data cache object"), + + INIT_PARAM(defer_registration, "defer system registration (for sampling)"), + INIT_PARAM(exitOnError, "exit on error"), + INIT_PARAM_DFLT(warnOnlyOnLoadError, "warn, but don't exit, if a load " + "result errors", false), + INIT_PARAM(function_trace, "Enable function trace"), + INIT_PARAM(function_trace_start, "Cycle to start function trace") + +END_INIT_SIM_OBJECT_PARAMS(OzoneChecker) + + +CREATE_SIM_OBJECT(OzoneChecker) +{ + OzoneChecker::Params *params = new OzoneChecker::Params(); + params->name = getInstanceName(); + params->numberOfThreads = 1; + params->max_insts_any_thread = 0; + params->max_insts_all_threads = 0; + params->max_loads_any_thread = 0; + params->max_loads_all_threads = 0; + params->exitOnError = exitOnError; + params->warnOnlyOnLoadError = warnOnlyOnLoadError; + params->deferRegistration = defer_registration; + params->functionTrace = function_trace; + params->functionTraceStart = function_trace_start; + params->clock = clock; + // Hack to touch all parameters. Consider not deriving Checker + // from BaseCPU..it's not really a CPU in the end. + Counter temp; + temp = max_insts_any_thread; + temp = max_insts_all_threads; + temp = max_loads_any_thread; + temp = max_loads_all_threads; + BaseMem *cache = icache; + cache = dcache; + +#if FULL_SYSTEM + params->itb = itb; + params->dtb = dtb; + params->mem = mem; + params->system = system; + params->cpu_id = cpu_id; + params->profile = profile; +#else + params->process = workload; +#endif + + OzoneChecker *cpu = new OzoneChecker(params); + return cpu; +} + +REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker) diff --git a/src/cpu/cpu_models.py b/src/cpu/cpu_models.py index 1a9724ca6..e7ef9ab42 100644 --- a/src/cpu/cpu_models.py +++ b/src/cpu/cpu_models.py @@ -67,7 +67,7 @@ CpuModel('TimingSimpleCPU', 'timing_simple_cpu_exec.cc', CpuModel('FullCPU', 'full_cpu_exec.cc', '#include "encumbered/cpu/full/dyn_inst.hh"', { 'CPU_exec_context': 'DynInst' }) -CpuModel('AlphaFullCPU', 'alpha_o3_exec.cc', +CpuModel('AlphaO3CPU', 'alpha_o3_exec.cc', '#include "cpu/o3/alpha_dyn_inst.hh"', { 'CPU_exec_context': 'AlphaDynInst' }) CpuModel('OzoneSimpleCPU', 'ozone_simple_exec.cc', diff --git a/src/cpu/o3/alpha_cpu.cc b/src/cpu/o3/alpha_cpu.cc index 39cae696b..e44ed0031 100644 --- a/src/cpu/o3/alpha_cpu.cc +++ b/src/cpu/o3/alpha_cpu.cc @@ -32,7 +32,7 @@ #include "cpu/o3/alpha_cpu_impl.hh" #include "cpu/o3/alpha_dyn_inst.hh" -// Force instantiation of AlphaFullCPU for all the implemntations that are +// Force instantiation of AlphaO3CPU for all the implemntations that are // needed. Consider merging this and alpha_dyn_inst.cc, and maybe all // classes that depend on a certain impl, into one file (alpha_impl.cc?). -template class AlphaFullCPU; +template class AlphaO3CPU; diff --git a/src/cpu/o3/alpha_cpu.hh b/src/cpu/o3/alpha_cpu.hh index f81837f3c..4daa8b3ba 100644 --- a/src/cpu/o3/alpha_cpu.hh +++ b/src/cpu/o3/alpha_cpu.hh @@ -44,7 +44,7 @@ namespace Kernel { class TranslatingPort; /** - * AlphaFullCPU class. Derives from the FullO3CPU class, and + * AlphaO3CPU class. Derives from the FullO3CPU class, and * implements all ISA and implementation specific functions of the * CPU. This is the CPU class that is used for the SimObjects, and is * what is given to the DynInsts. Most of its state exists in the @@ -52,7 +52,7 @@ class TranslatingPort; * functionality. */ template -class AlphaFullCPU : public FullO3CPU +class AlphaO3CPU : public FullO3CPU { protected: typedef TheISA::IntReg IntReg; @@ -67,17 +67,17 @@ class AlphaFullCPU : public FullO3CPU typedef O3ThreadState Thread; typedef typename Impl::Params Params; - /** Constructs an AlphaFullCPU with the given parameters. */ - AlphaFullCPU(Params *params); + /** Constructs an AlphaO3CPU with the given parameters. */ + AlphaO3CPU(Params *params); /** - * Derived ThreadContext class for use with the AlphaFullCPU. It + * Derived ThreadContext class for use with the AlphaO3CPU. It * provides the interface for any external objects to access a * single thread's state and some general CPU state. Any time * external objects try to update state through this interface, * the CPU will create an event to squash all in-flight * instructions in order to ensure state is maintained correctly. - * It must be defined specifically for the AlphaFullCPU because + * It must be defined specifically for the AlphaO3CPU because * not all architectural state is located within the O3ThreadState * (such as the commit PC, and registers), and specific actions * must be taken when using this interface (such as squashing all @@ -87,7 +87,7 @@ class AlphaFullCPU : public FullO3CPU { public: /** Pointer to the CPU. */ - AlphaFullCPU *cpu; + AlphaO3CPU *cpu; /** Pointer to the thread state that this TC corrseponds to. */ O3ThreadState *thread; diff --git a/src/cpu/o3/alpha_cpu_builder.cc b/src/cpu/o3/alpha_cpu_builder.cc index a6fbe34d7..b1e141ff4 100644 --- a/src/cpu/o3/alpha_cpu_builder.cc +++ b/src/cpu/o3/alpha_cpu_builder.cc @@ -37,15 +37,15 @@ #include "cpu/o3/fu_pool.hh" #include "sim/builder.hh" -class DerivAlphaFullCPU : public AlphaFullCPU +class DerivAlphaO3CPU : public AlphaO3CPU { public: - DerivAlphaFullCPU(AlphaSimpleParams *p) - : AlphaFullCPU(p) + DerivAlphaO3CPU(AlphaSimpleParams *p) + : AlphaO3CPU(p) { } }; -BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) +BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU) Param clock; Param numThreads; @@ -144,9 +144,9 @@ Param defer_registration; Param function_trace; Param function_trace_start; -END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) +END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaO3CPU) -BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) +BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU) INIT_PARAM(clock, "clock speed"), INIT_PARAM(numThreads, "number of HW thread contexts"), @@ -261,11 +261,11 @@ BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) INIT_PARAM(function_trace, "Enable function trace"), INIT_PARAM(function_trace_start, "Cycle to start function trace") -END_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU) +END_INIT_SIM_OBJECT_PARAMS(DerivAlphaO3CPU) -CREATE_SIM_OBJECT(DerivAlphaFullCPU) +CREATE_SIM_OBJECT(DerivAlphaO3CPU) { - DerivAlphaFullCPU *cpu; + DerivAlphaO3CPU *cpu; #if FULL_SYSTEM // Full-system only supports a single thread for the moment. @@ -386,10 +386,10 @@ CREATE_SIM_OBJECT(DerivAlphaFullCPU) params->functionTrace = function_trace; params->functionTraceStart = function_trace_start; - cpu = new DerivAlphaFullCPU(params); + cpu = new DerivAlphaO3CPU(params); return cpu; } -REGISTER_SIM_OBJECT("DerivAlphaFullCPU", DerivAlphaFullCPU) +REGISTER_SIM_OBJECT("DerivAlphaO3CPU", DerivAlphaO3CPU) diff --git a/src/cpu/o3/alpha_cpu_impl.hh b/src/cpu/o3/alpha_cpu_impl.hh index bfd05d260..532611fb6 100644 --- a/src/cpu/o3/alpha_cpu_impl.hh +++ b/src/cpu/o3/alpha_cpu_impl.hh @@ -28,6 +28,8 @@ * Authors: Kevin Lim */ +#include "config/use_checker.hh" + #include "arch/alpha/faults.hh" #include "base/cprintf.hh" #include "base/statistics.hh" @@ -53,14 +55,14 @@ using namespace TheISA; template -AlphaFullCPU::AlphaFullCPU(Params *params) +AlphaO3CPU::AlphaO3CPU(Params *params) #if FULL_SYSTEM : FullO3CPU(params), itb(params->itb), dtb(params->dtb) #else : FullO3CPU(params) #endif { - DPRINTF(FullCPU, "AlphaFullCPU: Creating AlphaFullCPU object.\n"); + DPRINTF(O3CPU, "Creating AlphaO3CPU object.\n"); // Setup any thread state. this->thread.resize(this->numThreads); @@ -73,7 +75,7 @@ AlphaFullCPU::AlphaFullCPU(Params *params) this->thread[i]->setStatus(ThreadContext::Suspended); #else if (i < params->workload.size()) { - DPRINTF(FullCPU, "FullCPU: Workload[%i] process is %#x", + DPRINTF(O3CPU, "Workload[%i] process is %#x", i, this->thread[i]); this->thread[i] = new Thread(this, i, params->workload[i], i, params->mem); @@ -110,14 +112,16 @@ AlphaFullCPU::AlphaFullCPU(Params *params) // Setup the TC that will serve as the interface to the threads/CPU. AlphaTC *alpha_tc = new AlphaTC; + tc = alpha_tc; + // If we're using a checker, then the TC should be the // CheckerThreadContext. +#if USE_CHECKER if (params->checker) { tc = new CheckerThreadContext( alpha_tc, this->checker); - } else { - tc = alpha_tc; } +#endif alpha_tc->cpu = this; alpha_tc->thread = this->thread[i]; @@ -172,7 +176,7 @@ AlphaFullCPU::AlphaFullCPU(Params *params) template void -AlphaFullCPU::regStats() +AlphaO3CPU::regStats() { // Register stats for everything that has stats. this->fullCPURegStats(); @@ -186,7 +190,7 @@ AlphaFullCPU::regStats() #if FULL_SYSTEM template VirtualPort * -AlphaFullCPU::AlphaTC::getVirtPort(ThreadContext *src_tc) +AlphaO3CPU::AlphaTC::getVirtPort(ThreadContext *src_tc) { if (!src_tc) return thread->getVirtPort(); @@ -203,7 +207,7 @@ AlphaFullCPU::AlphaTC::getVirtPort(ThreadContext *src_tc) template void -AlphaFullCPU::AlphaTC::dumpFuncProfile() +AlphaO3CPU::AlphaTC::dumpFuncProfile() { // Currently not supported } @@ -211,7 +215,7 @@ AlphaFullCPU::AlphaTC::dumpFuncProfile() template void -AlphaFullCPU::AlphaTC::takeOverFrom(ThreadContext *old_context) +AlphaO3CPU::AlphaTC::takeOverFrom(ThreadContext *old_context) { // some things should already be set up #if FULL_SYSTEM @@ -253,7 +257,7 @@ AlphaFullCPU::AlphaTC::takeOverFrom(ThreadContext *old_context) #if FULL_SYSTEM template void -AlphaFullCPU::AlphaTC::delVirtPort(VirtualPort *vp) +AlphaO3CPU::AlphaTC::delVirtPort(VirtualPort *vp) { delete vp->getPeer(); delete vp; @@ -262,9 +266,9 @@ AlphaFullCPU::AlphaTC::delVirtPort(VirtualPort *vp) template void -AlphaFullCPU::AlphaTC::activate(int delay) +AlphaO3CPU::AlphaTC::activate(int delay) { - DPRINTF(FullCPU, "Calling activate on AlphaTC\n"); + DPRINTF(O3CPU, "Calling activate on AlphaTC\n"); if (thread->status() == ThreadContext::Active) return; @@ -286,9 +290,9 @@ AlphaFullCPU::AlphaTC::activate(int delay) template void -AlphaFullCPU::AlphaTC::suspend() +AlphaO3CPU::AlphaTC::suspend() { - DPRINTF(FullCPU, "Calling suspend on AlphaTC\n"); + DPRINTF(O3CPU, "Calling suspend on AlphaTC\n"); if (thread->status() == ThreadContext::Suspended) return; @@ -312,9 +316,9 @@ AlphaFullCPU::AlphaTC::suspend() template void -AlphaFullCPU::AlphaTC::deallocate() +AlphaO3CPU::AlphaTC::deallocate() { - DPRINTF(FullCPU, "Calling deallocate on AlphaTC\n"); + DPRINTF(O3CPU, "Calling deallocate on AlphaTC\n"); if (thread->status() == ThreadContext::Unallocated) return; @@ -325,9 +329,9 @@ AlphaFullCPU::AlphaTC::deallocate() template void -AlphaFullCPU::AlphaTC::halt() +AlphaO3CPU::AlphaTC::halt() { - DPRINTF(FullCPU, "Calling halt on AlphaTC\n"); + DPRINTF(O3CPU, "Calling halt on AlphaTC\n"); if (thread->status() == ThreadContext::Halted) return; @@ -338,7 +342,7 @@ AlphaFullCPU::AlphaTC::halt() template void -AlphaFullCPU::AlphaTC::regStats(const std::string &name) +AlphaO3CPU::AlphaTC::regStats(const std::string &name) { #if FULL_SYSTEM thread->kernelStats = new Kernel::Statistics(cpu->system); @@ -348,7 +352,7 @@ AlphaFullCPU::AlphaTC::regStats(const std::string &name) template void -AlphaFullCPU::AlphaTC::serialize(std::ostream &os) +AlphaO3CPU::AlphaTC::serialize(std::ostream &os) { #if FULL_SYSTEM if (thread->kernelStats) @@ -359,7 +363,7 @@ AlphaFullCPU::AlphaTC::serialize(std::ostream &os) template void -AlphaFullCPU::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion) +AlphaO3CPU::AlphaTC::unserialize(Checkpoint *cp, const std::string §ion) { #if FULL_SYSTEM if (thread->kernelStats) @@ -371,46 +375,46 @@ AlphaFullCPU::AlphaTC::unserialize(Checkpoint *cp, const std::string § #if FULL_SYSTEM template EndQuiesceEvent * -AlphaFullCPU::AlphaTC::getQuiesceEvent() +AlphaO3CPU::AlphaTC::getQuiesceEvent() { return thread->quiesceEvent; } template Tick -AlphaFullCPU::AlphaTC::readLastActivate() +AlphaO3CPU::AlphaTC::readLastActivate() { return thread->lastActivate; } template Tick -AlphaFullCPU::AlphaTC::readLastSuspend() +AlphaO3CPU::AlphaTC::readLastSuspend() { return thread->lastSuspend; } template void -AlphaFullCPU::AlphaTC::profileClear() +AlphaO3CPU::AlphaTC::profileClear() {} template void -AlphaFullCPU::AlphaTC::profileSample() +AlphaO3CPU::AlphaTC::profileSample() {} #endif template TheISA::MachInst -AlphaFullCPU::AlphaTC:: getInst() +AlphaO3CPU::AlphaTC:: getInst() { return thread->getInst(); } template void -AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) +AlphaO3CPU::AlphaTC::copyArchRegs(ThreadContext *tc) { // This function will mess things up unless the ROB is empty and // there are no instructions in the pipeline. @@ -421,7 +425,7 @@ AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) for (int i = 0; i < AlphaISA::NumIntRegs; ++i) { renamed_reg = cpu->renameMap[tid].lookup(i); - DPRINTF(FullCPU, "FullCPU: Copying over register %i, had data %lli, " + DPRINTF(O3CPU, "Copying over register %i, had data %lli, " "now has data %lli.\n", renamed_reg, cpu->readIntReg(renamed_reg), tc->readIntReg(i)); @@ -449,19 +453,19 @@ AlphaFullCPU::AlphaTC::copyArchRegs(ThreadContext *tc) template void -AlphaFullCPU::AlphaTC::clearArchRegs() +AlphaO3CPU::AlphaTC::clearArchRegs() {} template uint64_t -AlphaFullCPU::AlphaTC::readIntReg(int reg_idx) +AlphaO3CPU::AlphaTC::readIntReg(int reg_idx) { return cpu->readArchIntReg(reg_idx, thread->readTid()); } template FloatReg -AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx, int width) +AlphaO3CPU::AlphaTC::readFloatReg(int reg_idx, int width) { switch(width) { case 32: @@ -476,14 +480,14 @@ AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx, int width) template FloatReg -AlphaFullCPU::AlphaTC::readFloatReg(int reg_idx) +AlphaO3CPU::AlphaTC::readFloatReg(int reg_idx) { return cpu->readArchFloatRegSingle(reg_idx, thread->readTid()); } template FloatRegBits -AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx, int width) +AlphaO3CPU::AlphaTC::readFloatRegBits(int reg_idx, int width) { DPRINTF(Fault, "Reading floatint register through the TC!\n"); return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); @@ -491,14 +495,14 @@ AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx, int width) template FloatRegBits -AlphaFullCPU::AlphaTC::readFloatRegBits(int reg_idx) +AlphaO3CPU::AlphaTC::readFloatRegBits(int reg_idx) { return cpu->readArchFloatRegInt(reg_idx, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) +AlphaO3CPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) { cpu->setArchIntReg(reg_idx, val, thread->readTid()); @@ -510,7 +514,7 @@ AlphaFullCPU::AlphaTC::setIntReg(int reg_idx, uint64_t val) template void -AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) +AlphaO3CPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) { switch(width) { case 32: @@ -529,7 +533,7 @@ AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val, int width) template void -AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) +AlphaO3CPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) { cpu->setArchFloatRegSingle(reg_idx, val, thread->readTid()); @@ -540,7 +544,7 @@ AlphaFullCPU::AlphaTC::setFloatReg(int reg_idx, FloatReg val) template void -AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, +AlphaO3CPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, int width) { DPRINTF(Fault, "Setting floatint register through the TC!\n"); @@ -554,7 +558,7 @@ AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val, template void -AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) +AlphaO3CPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) { cpu->setArchFloatRegInt(reg_idx, val, thread->readTid()); @@ -566,7 +570,7 @@ AlphaFullCPU::AlphaTC::setFloatRegBits(int reg_idx, FloatRegBits val) template void -AlphaFullCPU::AlphaTC::setPC(uint64_t val) +AlphaO3CPU::AlphaTC::setPC(uint64_t val) { cpu->setPC(val, thread->readTid()); @@ -578,7 +582,7 @@ AlphaFullCPU::AlphaTC::setPC(uint64_t val) template void -AlphaFullCPU::AlphaTC::setNextPC(uint64_t val) +AlphaO3CPU::AlphaTC::setNextPC(uint64_t val) { cpu->setNextPC(val, thread->readTid()); @@ -590,7 +594,7 @@ AlphaFullCPU::AlphaTC::setNextPC(uint64_t val) template Fault -AlphaFullCPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) +AlphaO3CPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) { Fault ret_fault = cpu->setMiscReg(misc_reg, val, thread->readTid()); @@ -604,8 +608,8 @@ AlphaFullCPU::AlphaTC::setMiscReg(int misc_reg, const MiscReg &val) template Fault -AlphaFullCPU::AlphaTC::setMiscRegWithEffect(int misc_reg, - const MiscReg &val) +AlphaO3CPU::AlphaTC::setMiscRegWithEffect(int misc_reg, + const MiscReg &val) { Fault ret_fault = cpu->setMiscRegWithEffect(misc_reg, val, thread->readTid()); @@ -622,21 +626,21 @@ AlphaFullCPU::AlphaTC::setMiscRegWithEffect(int misc_reg, template TheISA::IntReg -AlphaFullCPU::AlphaTC::getSyscallArg(int i) +AlphaO3CPU::AlphaTC::getSyscallArg(int i) { return cpu->getSyscallArg(i, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setSyscallArg(int i, IntReg val) +AlphaO3CPU::AlphaTC::setSyscallArg(int i, IntReg val) { cpu->setSyscallArg(i, val, thread->readTid()); } template void -AlphaFullCPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) +AlphaO3CPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) { cpu->setSyscallReturn(return_value, thread->readTid()); } @@ -645,37 +649,37 @@ AlphaFullCPU::AlphaTC::setSyscallReturn(SyscallReturn return_value) template MiscReg -AlphaFullCPU::readMiscReg(int misc_reg, unsigned tid) +AlphaO3CPU::readMiscReg(int misc_reg, unsigned tid) { return this->regFile.readMiscReg(misc_reg, tid); } template MiscReg -AlphaFullCPU::readMiscRegWithEffect(int misc_reg, Fault &fault, - unsigned tid) +AlphaO3CPU::readMiscRegWithEffect(int misc_reg, Fault &fault, + unsigned tid) { return this->regFile.readMiscRegWithEffect(misc_reg, fault, tid); } template Fault -AlphaFullCPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) +AlphaO3CPU::setMiscReg(int misc_reg, const MiscReg &val, unsigned tid) { return this->regFile.setMiscReg(misc_reg, val, tid); } template Fault -AlphaFullCPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, - unsigned tid) +AlphaO3CPU::setMiscRegWithEffect(int misc_reg, const MiscReg &val, + unsigned tid) { return this->regFile.setMiscRegWithEffect(misc_reg, val, tid); } template void -AlphaFullCPU::squashFromTC(unsigned tid) +AlphaO3CPU::squashFromTC(unsigned tid) { this->thread[tid]->inSyscall = true; this->commit.generateTCEvent(tid); @@ -685,7 +689,7 @@ AlphaFullCPU::squashFromTC(unsigned tid) template void -AlphaFullCPU::post_interrupt(int int_num, int index) +AlphaO3CPU::post_interrupt(int int_num, int index) { BaseCPU::post_interrupt(int_num, index); @@ -697,21 +701,21 @@ AlphaFullCPU::post_interrupt(int int_num, int index) template int -AlphaFullCPU::readIntrFlag() +AlphaO3CPU::readIntrFlag() { return this->regFile.readIntrFlag(); } template void -AlphaFullCPU::setIntrFlag(int val) +AlphaO3CPU::setIntrFlag(int val) { this->regFile.setIntrFlag(val); } template Fault -AlphaFullCPU::hwrei(unsigned tid) +AlphaO3CPU::hwrei(unsigned tid) { // Need to clear the lock flag upon returning from an interrupt. this->lockFlag = false; @@ -726,7 +730,7 @@ AlphaFullCPU::hwrei(unsigned tid) template bool -AlphaFullCPU::simPalCheck(int palFunc, unsigned tid) +AlphaO3CPU::simPalCheck(int palFunc, unsigned tid) { if (this->thread[tid]->kernelStats) this->thread[tid]->kernelStats->callpal(palFunc, @@ -751,7 +755,7 @@ AlphaFullCPU::simPalCheck(int palFunc, unsigned tid) template void -AlphaFullCPU::trap(Fault fault, unsigned tid) +AlphaO3CPU::trap(Fault fault, unsigned tid) { // Pass the thread's TC into the invoke method. fault->invoke(this->threadContexts[tid]); @@ -759,7 +763,7 @@ AlphaFullCPU::trap(Fault fault, unsigned tid) template void -AlphaFullCPU::processInterrupts() +AlphaO3CPU::processInterrupts() { // Check for interrupts here. For now can copy the code that // exists within isa_fullsys_traits.hh. Also assume that thread 0 @@ -805,10 +809,12 @@ AlphaFullCPU::processInterrupts() this->setMiscReg(IPR_ISR, summary, 0); this->setMiscReg(IPR_INTID, ipl, 0); // Checker needs to know these two registers were updated. +#if USE_CHECKER if (this->checker) { this->checker->threadBase()->setMiscReg(IPR_ISR, summary); this->checker->threadBase()->setMiscReg(IPR_INTID, ipl); } +#endif this->trap(Fault(new InterruptFault), 0); DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n", this->readMiscReg(IPR_IPLR, 0), ipl, summary); @@ -821,9 +827,9 @@ AlphaFullCPU::processInterrupts() template void -AlphaFullCPU::syscall(int64_t callnum, int tid) +AlphaO3CPU::syscall(int64_t callnum, int tid) { - DPRINTF(FullCPU, "AlphaFullCPU: [tid:%i] Executing syscall().\n\n", tid); + DPRINTF(O3CPU, "[tid:%i] Executing syscall().\n\n", tid); DPRINTF(Activity,"Activity: syscall() called.\n"); @@ -841,21 +847,21 @@ AlphaFullCPU::syscall(int64_t callnum, int tid) template TheISA::IntReg -AlphaFullCPU::getSyscallArg(int i, int tid) +AlphaO3CPU::getSyscallArg(int i, int tid) { return this->readArchIntReg(AlphaISA::ArgumentReg0 + i, tid); } template void -AlphaFullCPU::setSyscallArg(int i, IntReg val, int tid) +AlphaO3CPU::setSyscallArg(int i, IntReg val, int tid) { this->setArchIntReg(AlphaISA::ArgumentReg0 + i, val, tid); } template void -AlphaFullCPU::setSyscallReturn(SyscallReturn return_value, int tid) +AlphaO3CPU::setSyscallReturn(SyscallReturn return_value, int tid) { // check for error condition. Alpha syscall convention is to // indicate success/failure in reg a3 (r19) and put the diff --git a/src/cpu/o3/alpha_dyn_inst.hh b/src/cpu/o3/alpha_dyn_inst.hh index 36a08c4a7..464e53e9d 100644 --- a/src/cpu/o3/alpha_dyn_inst.hh +++ b/src/cpu/o3/alpha_dyn_inst.hh @@ -51,7 +51,7 @@ class AlphaDynInst : public BaseDynInst { public: /** Typedef for the CPU. */ - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; /** Binary machine instruction type. */ typedef TheISA::MachInst MachInst; @@ -74,7 +74,7 @@ class AlphaDynInst : public BaseDynInst public: /** BaseDynInst constructor given a binary instruction. */ AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, InstSeqNum seq_num, - FullCPU *cpu); + O3CPU *cpu); /** BaseDynInst constructor given a static inst pointer. */ AlphaDynInst(StaticInstPtr &_staticInst); diff --git a/src/cpu/o3/alpha_dyn_inst_impl.hh b/src/cpu/o3/alpha_dyn_inst_impl.hh index a73cf4a7d..6183a755e 100644 --- a/src/cpu/o3/alpha_dyn_inst_impl.hh +++ b/src/cpu/o3/alpha_dyn_inst_impl.hh @@ -32,7 +32,7 @@ template AlphaDynInst::AlphaDynInst(ExtMachInst inst, Addr PC, Addr Pred_PC, - InstSeqNum seq_num, FullCPU *cpu) + InstSeqNum seq_num, O3CPU *cpu) : BaseDynInst(inst, PC, Pred_PC, seq_num, cpu) { initVars(); diff --git a/src/cpu/o3/alpha_impl.hh b/src/cpu/o3/alpha_impl.hh index 52f7c2394..84c9e1c00 100644 --- a/src/cpu/o3/alpha_impl.hh +++ b/src/cpu/o3/alpha_impl.hh @@ -41,12 +41,12 @@ template class AlphaDynInst; template -class AlphaFullCPU; +class AlphaO3CPU; /** Implementation specific struct that defines several key types to the * CPU, the stages within the CPU, the time buffers, and the DynInst. * The struct defines the ISA, the CPU policy, the specific DynInst, the - * specific FullCPU, and all of the structs from the time buffers to do + * specific O3CPU, and all of the structs from the time buffers to do * communication. * This is one of the key things that must be defined for each hardware * specific CPU implementation. @@ -67,8 +67,14 @@ struct AlphaSimpleImpl */ typedef RefCountingPtr DynInstPtr; - /** The FullCPU type to be used. */ - typedef AlphaFullCPU FullCPU; + /** The O3CPU type to be used. */ + typedef AlphaO3CPU O3CPU; + + /** Same typedef, but for CPUType. BaseDynInst may not always use + * an O3 CPU, so it's clearer to call it CPUType instead in that + * case. + */ + typedef O3CPU CPUType; /** The Params to be passed to each stage. */ typedef AlphaSimpleParams Params; diff --git a/src/cpu/o3/alpha_params.hh b/src/cpu/o3/alpha_params.hh index 2ece7fb7f..f0732733e 100644 --- a/src/cpu/o3/alpha_params.hh +++ b/src/cpu/o3/alpha_params.hh @@ -42,12 +42,12 @@ class Process; class System; /** - * This file defines the parameters that will be used for the AlphaFullCPU. + * This file defines the parameters that will be used for the AlphaO3CPU. * This must be defined externally so that the Impl can have a params class * defined that it can pass to all of the individual stages. */ -class AlphaSimpleParams : public BaseFullCPU::Params +class AlphaSimpleParams : public BaseO3CPU::Params { public: diff --git a/src/cpu/o3/commit.hh b/src/cpu/o3/commit.hh index 0b31cb9c8..1c0cd1037 100644 --- a/src/cpu/o3/commit.hh +++ b/src/cpu/o3/commit.hh @@ -67,7 +67,7 @@ class DefaultCommit { public: // Typedefs from the Impl. - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; typedef typename Impl::CPUPol CPUPol; @@ -145,7 +145,7 @@ class DefaultCommit void regStats(); /** Sets the CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the list of threads. */ void setThreads(std::vector &threads); @@ -317,8 +317,8 @@ class DefaultCommit ROB *rob; private: - /** Pointer to FullCPU. */ - FullCPU *cpu; + /** Pointer to O3CPU. */ + O3CPU *cpu; /** Vector of all of the threads. */ std::vector thread; diff --git a/src/cpu/o3/commit_impl.hh b/src/cpu/o3/commit_impl.hh index a18271918..566324b69 100644 --- a/src/cpu/o3/commit_impl.hh +++ b/src/cpu/o3/commit_impl.hh @@ -28,6 +28,9 @@ * Authors: Kevin Lim */ +#include "config/full_system.hh" +#include "config/use_checker.hh" + #include #include @@ -219,14 +222,14 @@ DefaultCommit::regStats() template void -DefaultCommit::setCPU(FullCPU *cpu_ptr) +DefaultCommit::setCPU(O3CPU *cpu_ptr) { DPRINTF(Commit, "Commit: Setting CPU pointer.\n"); cpu = cpu_ptr; // Commit must broadcast the number of free entries it has at the start of // the simulation, so it starts as active. - cpu->activateStage(FullCPU::CommitIdx); + cpu->activateStage(O3CPU::CommitIdx); trapLatency = cpu->cycles(trapLatency); fetchTrapLatency = cpu->cycles(fetchTrapLatency); @@ -395,10 +398,10 @@ DefaultCommit::updateStatus() if (_nextStatus == Inactive && _status == Active) { DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::CommitIdx); + cpu->deactivateStage(O3CPU::CommitIdx); } else if (_nextStatus == Active && _status == Inactive) { DPRINTF(Activity, "Activating stage.\n"); - cpu->activateStage(FullCPU::CommitIdx); + cpu->activateStage(O3CPU::CommitIdx); } _status = _nextStatus; @@ -972,11 +975,13 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) head_inst->setCompleted(); } +#if USE_CHECKER // Use checker prior to updating anything due to traps or PC // based events. if (cpu->checker) { cpu->checker->verify(head_inst); } +#endif // Check if the instruction caused a fault. If so, trap. Fault inst_fault = head_inst->getFault(); @@ -992,9 +997,11 @@ DefaultCommit::commitHead(DynInstPtr &head_inst, unsigned inst_num) return false; } +#if USE_CHECKER if (cpu->checker && head_inst->isStore()) { cpu->checker->verify(head_inst); } +#endif assert(!thread[tid]->inSyscall); diff --git a/src/cpu/o3/cpu.cc b/src/cpu/o3/cpu.cc index 788c6b164..430078860 100644 --- a/src/cpu/o3/cpu.cc +++ b/src/cpu/o3/cpu.cc @@ -29,6 +29,7 @@ */ #include "config/full_system.hh" +#include "config/use_checker.hh" #if FULL_SYSTEM #include "sim/system.hh" @@ -50,13 +51,13 @@ using namespace std; using namespace TheISA; -BaseFullCPU::BaseFullCPU(Params *params) +BaseO3CPU::BaseO3CPU(Params *params) : BaseCPU(params), cpu_id(0) { } void -BaseFullCPU::regStats() +BaseO3CPU::regStats() { BaseCPU::regStats(); } @@ -83,7 +84,7 @@ FullO3CPU::TickEvent::description() template FullO3CPU::FullO3CPU(Params *params) - : BaseFullCPU(params), + : BaseO3CPU(params), tickEvent(this), removeInstsThisCycle(false), fetch(params), @@ -131,6 +132,9 @@ FullO3CPU::FullO3CPU(Params *params) { _status = Idle; + checker = NULL; + +#if USE_CHECKER if (params->checker) { BaseCPU *temp_checker = params->checker; checker = dynamic_cast *>(temp_checker); @@ -138,9 +142,8 @@ FullO3CPU::FullO3CPU(Params *params) #if FULL_SYSTEM checker->setSystem(params->system); #endif - } else { - checker = NULL; } +#endif #if !FULL_SYSTEM thread.resize(number_of_threads); @@ -261,9 +264,9 @@ template void FullO3CPU::fullCPURegStats() { - BaseFullCPU::regStats(); + BaseO3CPU::regStats(); - // Register any of the FullCPU's stats here. + // Register any of the O3CPU's stats here. timesIdled .name(name() + ".timesIdled") .desc("Number of times that the entire CPU went into an idle state and" @@ -319,7 +322,7 @@ template void FullO3CPU::tick() { - DPRINTF(FullCPU, "\n\nFullCPU: Ticking main, FullO3CPU.\n"); + DPRINTF(O3CPU, "\n\nFullO3CPU: Ticking main, FullO3CPU.\n"); ++numCycles; @@ -418,7 +421,7 @@ template void FullO3CPU::insertThread(unsigned tid) { - DPRINTF(FullCPU,"[tid:%i] Initializing thread data"); + DPRINTF(O3CPU,"[tid:%i] Initializing thread data"); // Will change now that the PC and thread state is internal to the CPU // and not in the ThreadContext. #if 0 @@ -465,7 +468,7 @@ template void FullO3CPU::removeThread(unsigned tid) { - DPRINTF(FullCPU,"[tid:%i] Removing thread data"); + DPRINTF(O3CPU,"[tid:%i] Removing thread data"); #if 0 //Unbind Int Regs from Rename Map for (int ireg = 0; ireg < TheISA::NumIntRegs; ireg++) { @@ -511,37 +514,37 @@ template void FullO3CPU::activateWhenReady(int tid) { - DPRINTF(FullCPU,"[tid:%i]: Checking if resources are available for incoming" + DPRINTF(O3CPU,"[tid:%i]: Checking if resources are available for incoming" "(e.g. PhysRegs/ROB/IQ/LSQ) \n", tid); bool ready = true; if (freeList.numFreeIntRegs() >= TheISA::NumIntRegs) { - DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "Phys. Int. Regs.\n", tid); ready = false; } else if (freeList.numFreeFloatRegs() >= TheISA::NumFloatRegs) { - DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "Phys. Float. Regs.\n", tid); ready = false; } else if (commit.rob->numFreeEntries() >= commit.rob->entryAmount(activeThreads.size() + 1)) { - DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "ROB entries.\n", tid); ready = false; } else if (iew.instQueue.numFreeEntries() >= iew.instQueue.entryAmount(activeThreads.size() + 1)) { - DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "IQ entries.\n", tid); ready = false; } else if (iew.ldstQueue.numFreeEntries() >= iew.ldstQueue.entryAmount(activeThreads.size() + 1)) { - DPRINTF(FullCPU,"[tid:%i] Suspending thread due to not enough " + DPRINTF(O3CPU,"[tid:%i] Suspending thread due to not enough " "LSQ entries.\n", tid); ready = false; @@ -575,7 +578,7 @@ FullO3CPU::activateContext(int tid, int delay) if (isActive == activeThreads.end()) { //May Need to Re-code this if the delay variable is the //delay needed for thread to activate - DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", + DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", tid); activeThreads.push_back(tid); @@ -597,7 +600,7 @@ template void FullO3CPU::suspendContext(int tid) { - DPRINTF(FullCPU,"[tid: %i]: Suspended ...\n", tid); + DPRINTF(O3CPU,"[tid: %i]: Suspended ...\n", tid); unscheduleTickEvent(); _status = Idle; /* @@ -606,7 +609,7 @@ FullO3CPU::suspendContext(int tid) activeThreads.begin(), activeThreads.end(), tid); if (isActive != activeThreads.end()) { - DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", + DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", tid); activeThreads.erase(isActive); } @@ -617,14 +620,14 @@ template void FullO3CPU::deallocateContext(int tid) { - DPRINTF(FullCPU,"[tid:%i]: Deallocating ...", tid); + DPRINTF(O3CPU,"[tid:%i]: Deallocating ...", tid); /* //Remove From Active List, if Active list::iterator isActive = find( activeThreads.begin(), activeThreads.end(), tid); if (isActive != activeThreads.end()) { - DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", + DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", tid); activeThreads.erase(isActive); @@ -637,14 +640,14 @@ template void FullO3CPU::haltContext(int tid) { - DPRINTF(FullCPU,"[tid:%i]: Halted ...", tid); + DPRINTF(O3CPU,"[tid:%i]: Halted ...", tid); /* //Remove From Active List, if Active list::iterator isActive = find( activeThreads.begin(), activeThreads.end(), tid); if (isActive != activeThreads.end()) { - DPRINTF(FullCPU,"[tid:%i]: Removing from active threads list\n", + DPRINTF(O3CPU,"[tid:%i]: Removing from active threads list\n", tid); activeThreads.erase(isActive); @@ -730,7 +733,7 @@ FullO3CPU::takeOverFrom(BaseCPU *oldCPU) if (isActive == activeThreads.end()) { //May Need to Re-code this if the delay variable is the delay //needed for thread to activate - DPRINTF(FullCPU, "Adding Thread %i to active threads list\n", + DPRINTF(O3CPU, "Adding Thread %i to active threads list\n", tid); activeThreads.push_back(tid); @@ -958,7 +961,7 @@ template void FullO3CPU::removeFrontInst(DynInstPtr &inst) { - DPRINTF(FullCPU, "FullCPU: Removing committed instruction [tid:%i] PC %#x " + DPRINTF(O3CPU, "Removing committed instruction [tid:%i] PC %#x " "[sn:%lli]\n", inst->threadNumber, inst->readPC(), inst->seqNum); @@ -972,7 +975,7 @@ template void FullO3CPU::removeInstsNotInROB(unsigned tid) { - DPRINTF(FullCPU, "FullCPU: Thread %i: Deleting instructions from instruction" + DPRINTF(O3CPU, "Thread %i: Deleting instructions from instruction" " list.\n", tid); ListIt end_it; @@ -982,12 +985,12 @@ FullO3CPU::removeInstsNotInROB(unsigned tid) if (instList.empty()) { return; } else if (rob.isEmpty(/*tid*/)) { - DPRINTF(FullCPU, "FullCPU: ROB is empty, squashing all insts.\n"); + DPRINTF(O3CPU, "ROB is empty, squashing all insts.\n"); end_it = instList.begin(); rob_empty = true; } else { end_it = (rob.readTailInst(tid))->getInstListIt(); - DPRINTF(FullCPU, "FullCPU: ROB is not empty, squashing insts not in ROB.\n"); + DPRINTF(O3CPU, "ROB is not empty, squashing insts not in ROB.\n"); } removeInstsThisCycle = true; @@ -1026,7 +1029,7 @@ FullO3CPU::removeInstsUntil(const InstSeqNum &seq_num, inst_iter--; - DPRINTF(FullCPU, "FullCPU: Deleting instructions from instruction " + DPRINTF(O3CPU, "Deleting instructions from instruction " "list that are from [tid:%i] and above [sn:%lli] (end=%lli).\n", tid, seq_num, (*inst_iter)->seqNum); @@ -1048,7 +1051,7 @@ inline void FullO3CPU::squashInstIt(const ListIt &instIt, const unsigned &tid) { if ((*instIt)->threadNumber == tid) { - DPRINTF(FullCPU, "FullCPU: Squashing instruction, " + DPRINTF(O3CPU, "Squashing instruction, " "[tid:%i] [sn:%lli] PC %#x\n", (*instIt)->threadNumber, (*instIt)->seqNum, @@ -1069,7 +1072,7 @@ void FullO3CPU::cleanUpRemovedInsts() { while (!removeList.empty()) { - DPRINTF(FullCPU, "FullCPU: Removing instruction, " + DPRINTF(O3CPU, "Removing instruction, " "[tid:%i] [sn:%lli] PC %#x\n", (*removeList.front())->threadNumber, (*removeList.front())->seqNum, diff --git a/src/cpu/o3/cpu.hh b/src/cpu/o3/cpu.hh index ff41a3306..bd6870114 100644 --- a/src/cpu/o3/cpu.hh +++ b/src/cpu/o3/cpu.hh @@ -56,13 +56,13 @@ class ThreadContext; class MemObject; class Process; -class BaseFullCPU : public BaseCPU +class BaseO3CPU : public BaseCPU { //Stuff that's pretty ISA independent will go here. public: typedef BaseCPU::Params Params; - BaseFullCPU(Params *params); + BaseO3CPU(Params *params); void regStats(); @@ -78,7 +78,7 @@ class BaseFullCPU : public BaseCPU * tick() function for the CPU is defined here. */ template -class FullO3CPU : public BaseFullCPU +class FullO3CPU : public BaseO3CPU { public: typedef TheISA::FloatReg FloatReg; diff --git a/src/cpu/o3/decode.hh b/src/cpu/o3/decode.hh index ff88358d6..1edf3335d 100644 --- a/src/cpu/o3/decode.hh +++ b/src/cpu/o3/decode.hh @@ -48,7 +48,7 @@ class DefaultDecode { private: // Typedefs from the Impl. - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; typedef typename Impl::CPUPol CPUPol; @@ -95,7 +95,7 @@ class DefaultDecode void regStats(); /** Sets CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer *tb_ptr); @@ -189,7 +189,7 @@ class DefaultDecode private: // Interfaces to objects outside of decode. /** CPU interface. */ - FullCPU *cpu; + O3CPU *cpu; /** Time buffer interface. */ TimeBuffer *timeBuffer; diff --git a/src/cpu/o3/decode_impl.hh b/src/cpu/o3/decode_impl.hh index 48f6ee612..16be01784 100644 --- a/src/cpu/o3/decode_impl.hh +++ b/src/cpu/o3/decode_impl.hh @@ -112,7 +112,7 @@ DefaultDecode::regStats() template void -DefaultDecode::setCPU(FullCPU *cpu_ptr) +DefaultDecode::setCPU(O3CPU *cpu_ptr) { DPRINTF(Decode, "Setting CPU pointer.\n"); cpu = cpu_ptr; @@ -427,7 +427,7 @@ DefaultDecode::updateStatus() DPRINTF(Activity, "Activating stage.\n"); - cpu->activateStage(FullCPU::DecodeIdx); + cpu->activateStage(O3CPU::DecodeIdx); } } else { // If it's not unblocking, then decode will not have any internal @@ -436,7 +436,7 @@ DefaultDecode::updateStatus() _status = Inactive; DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::DecodeIdx); + cpu->deactivateStage(O3CPU::DecodeIdx); } } } diff --git a/src/cpu/o3/fetch.hh b/src/cpu/o3/fetch.hh index 962d46437..476d4343f 100644 --- a/src/cpu/o3/fetch.hh +++ b/src/cpu/o3/fetch.hh @@ -57,7 +57,7 @@ class DefaultFetch typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInst DynInst; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::Params Params; /** Typedefs from the CPU policy. */ @@ -164,7 +164,7 @@ class DefaultFetch void regStats(); /** Sets CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer *time_buffer); @@ -296,8 +296,8 @@ class DefaultFetch int branchCount(); private: - /** Pointer to the FullCPU. */ - FullCPU *cpu; + /** Pointer to the O3CPU. */ + O3CPU *cpu; /** Time buffer interface. */ TimeBuffer *timeBuffer; diff --git a/src/cpu/o3/fetch_impl.hh b/src/cpu/o3/fetch_impl.hh index 477a1469c..ab706ed47 100644 --- a/src/cpu/o3/fetch_impl.hh +++ b/src/cpu/o3/fetch_impl.hh @@ -28,6 +28,8 @@ * Authors: Kevin Lim */ +#include "config/use_checker.hh" + #include "arch/isa_traits.hh" #include "arch/utility.hh" #include "cpu/checker/cpu.hh" @@ -268,7 +270,7 @@ DefaultFetch::regStats() template void -DefaultFetch::setCPU(FullCPU *cpu_ptr) +DefaultFetch::setCPU(O3CPU *cpu_ptr) { DPRINTF(Fetch, "Setting the CPU pointer.\n"); cpu = cpu_ptr; @@ -280,9 +282,11 @@ DefaultFetch::setCPU(FullCPU *cpu_ptr) icachePort->setPeer(mem_dport); mem_dport->setPeer(icachePort); +#if USE_CHECKER if (cpu->checker) { cpu->checker->setIcachePort(icachePort); } +#endif // Fetch needs to start fetching instructions at the very beginning, // so it must start up in active state. @@ -430,7 +434,7 @@ DefaultFetch::switchToActive() if (_status == Inactive) { DPRINTF(Activity, "Activating stage.\n"); - cpu->activateStage(FullCPU::FetchIdx); + cpu->activateStage(O3CPU::FetchIdx); _status = Active; } @@ -443,7 +447,7 @@ DefaultFetch::switchToInactive() if (_status == Active) { DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::FetchIdx); + cpu->deactivateStage(O3CPU::FetchIdx); _status = Inactive; } @@ -662,7 +666,7 @@ DefaultFetch::updateFetchStatus() "completion\n",tid); } - cpu->activateStage(FullCPU::FetchIdx); + cpu->activateStage(O3CPU::FetchIdx); } return Active; @@ -673,7 +677,7 @@ DefaultFetch::updateFetchStatus() if (_status == Active) { DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::FetchIdx); + cpu->deactivateStage(O3CPU::FetchIdx); } return Inactive; diff --git a/src/cpu/o3/iew.hh b/src/cpu/o3/iew.hh index 615022dc9..2af68d8fc 100644 --- a/src/cpu/o3/iew.hh +++ b/src/cpu/o3/iew.hh @@ -68,7 +68,7 @@ class DefaultIEW //Typedefs from Impl typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::Params Params; typedef typename CPUPol::IQ IQ; @@ -80,7 +80,7 @@ class DefaultIEW typedef typename CPUPol::RenameStruct RenameStruct; typedef typename CPUPol::IssueStruct IssueStruct; - friend class Impl::FullCPU; + friend class Impl::O3CPU; friend class CPUPol::IQ; public: @@ -126,7 +126,7 @@ class DefaultIEW void initStage(); /** Sets CPU pointer for IEW, IQ, and LSQ. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets main time buffer used for backwards communication. */ void setTimeBuffer(TimeBuffer *tb_ptr); @@ -331,7 +331,7 @@ class DefaultIEW private: /** CPU pointer. */ - FullCPU *cpu; + O3CPU *cpu; /** Records if IEW has written to the time buffer this cycle, so that the * CPU can deschedule itself if there is no activity. diff --git a/src/cpu/o3/iew_impl.hh b/src/cpu/o3/iew_impl.hh index 6c207d94a..8e6fd46a1 100644 --- a/src/cpu/o3/iew_impl.hh +++ b/src/cpu/o3/iew_impl.hh @@ -276,7 +276,7 @@ DefaultIEW::initStage() template void -DefaultIEW::setCPU(FullCPU *cpu_ptr) +DefaultIEW::setCPU(O3CPU *cpu_ptr) { DPRINTF(IEW, "Setting CPU pointer.\n"); cpu = cpu_ptr; @@ -284,7 +284,7 @@ DefaultIEW::setCPU(FullCPU *cpu_ptr) instQueue.setCPU(cpu_ptr); ldstQueue.setCPU(cpu_ptr); - cpu->activateStage(FullCPU::IEWIdx); + cpu->activateStage(O3CPU::IEWIdx); } template @@ -857,7 +857,7 @@ inline void DefaultIEW::activateStage() { DPRINTF(Activity, "Activating stage.\n"); - cpu->activateStage(FullCPU::IEWIdx); + cpu->activateStage(O3CPU::IEWIdx); } template @@ -865,7 +865,7 @@ inline void DefaultIEW::deactivateStage() { DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::IEWIdx); + cpu->deactivateStage(O3CPU::IEWIdx); } template diff --git a/src/cpu/o3/inst_queue.hh b/src/cpu/o3/inst_queue.hh index 6fd3c6d0b..d745faf7b 100644 --- a/src/cpu/o3/inst_queue.hh +++ b/src/cpu/o3/inst_queue.hh @@ -68,7 +68,7 @@ class InstructionQueue { public: //Typedefs from the Impl. - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::Params Params; @@ -80,7 +80,7 @@ class InstructionQueue // Typedef of iterator through the list of instructions. typedef typename std::list::iterator ListIt; - friend class Impl::FullCPU; + friend class Impl::O3CPU; /** FU completion event class. */ class FUCompletion : public Event { @@ -125,7 +125,7 @@ class InstructionQueue void resetState(); /** Sets CPU pointer. */ - void setCPU(FullCPU *_cpu) { cpu = _cpu; } + void setCPU(O3CPU *_cpu) { cpu = _cpu; } /** Sets active threads list. */ void setActiveThreads(std::list *at_ptr); @@ -252,7 +252,7 @@ class InstructionQueue ///////////////////////// /** Pointer to the CPU. */ - FullCPU *cpu; + O3CPU *cpu; /** Cache interface. */ MemInterface *dcacheInterface; diff --git a/src/cpu/o3/lsq.hh b/src/cpu/o3/lsq.hh index 1dbd46b8e..89791fec9 100644 --- a/src/cpu/o3/lsq.hh +++ b/src/cpu/o3/lsq.hh @@ -44,7 +44,7 @@ template class LSQ { public: typedef typename Impl::Params Params; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::CPUPol::IEW IEW; typedef typename Impl::CPUPol::LSQUnit LSQUnit; @@ -68,7 +68,7 @@ class LSQ { /** Sets the pointer to the list of active threads. */ void setActiveThreads(std::list *at_ptr); /** Sets the CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the IEW stage pointer. */ void setIEW(IEW *iew_ptr); /** Switches out the LSQ. */ @@ -275,7 +275,7 @@ class LSQ { LSQUnit thread[Impl::MaxThreads]; /** The CPU pointer. */ - FullCPU *cpu; + O3CPU *cpu; /** The IEW stage pointer. */ IEW *iewStage; diff --git a/src/cpu/o3/lsq_impl.hh b/src/cpu/o3/lsq_impl.hh index 0b6c6f542..5173f8be1 100644 --- a/src/cpu/o3/lsq_impl.hh +++ b/src/cpu/o3/lsq_impl.hh @@ -126,7 +126,7 @@ LSQ::setActiveThreads(list *at_ptr) template void -LSQ::setCPU(FullCPU *cpu_ptr) +LSQ::setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; diff --git a/src/cpu/o3/lsq_unit.hh b/src/cpu/o3/lsq_unit.hh index 2d700ddf1..cef6e0a2e 100644 --- a/src/cpu/o3/lsq_unit.hh +++ b/src/cpu/o3/lsq_unit.hh @@ -61,7 +61,7 @@ class LSQUnit { typedef TheISA::IntReg IntReg; public: typedef typename Impl::Params Params; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef typename Impl::CPUPol::IEW IEW; typedef typename Impl::CPUPol::IssueStruct IssueStruct; @@ -81,7 +81,7 @@ class LSQUnit { void regStats(); /** Sets the CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the IEW stage pointer. */ void setIEW(IEW *iew_ptr) @@ -232,7 +232,7 @@ class LSQUnit { private: /** Pointer to the CPU. */ - FullCPU *cpu; + O3CPU *cpu; /** Pointer to the IEW stage. */ IEW *iewStage; @@ -249,13 +249,13 @@ class LSQUnit { { protected: /** Pointer to CPU. */ - FullCPU *cpu; + O3CPU *cpu; /** Pointer to LSQ. */ LSQUnit *lsq; public: /** Default constructor. */ - DcachePort(FullCPU *_cpu, LSQUnit *_lsq) + DcachePort(O3CPU *_cpu, LSQUnit *_lsq) : Port(_lsq->name() + "-dport"), cpu(_cpu), lsq(_lsq) { } diff --git a/src/cpu/o3/lsq_unit_impl.hh b/src/cpu/o3/lsq_unit_impl.hh index 6e201ea5f..f4a656aa1 100644 --- a/src/cpu/o3/lsq_unit_impl.hh +++ b/src/cpu/o3/lsq_unit_impl.hh @@ -29,6 +29,8 @@ * Korey Sewell */ +#include "config/use_checker.hh" + #include "cpu/checker/cpu.hh" #include "cpu/o3/lsq_unit.hh" #include "base/str.hh" @@ -171,7 +173,7 @@ LSQUnit::init(Params *params, unsigned maxLQEntries, template void -LSQUnit::setCPU(FullCPU *cpu_ptr) +LSQUnit::setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; dcachePort = new DcachePort(cpu, this); @@ -180,9 +182,11 @@ LSQUnit::setCPU(FullCPU *cpu_ptr) dcachePort->setPeer(mem_dport); mem_dport->setPeer(dcachePort); +#if USE_CHECKER if (cpu->checker) { cpu->checker->setDcachePort(dcachePort); } +#endif } template @@ -788,9 +792,11 @@ LSQUnit::storePostSend(Packet *pkt) // only works so long as the checker doesn't try to // verify the value in memory for stores. storeQueue[storeWBIdx].inst->setCompleted(); +#if USE_CHECKER if (cpu->checker) { cpu->checker->verify(storeQueue[storeWBIdx].inst); } +#endif } if (pkt->result != Packet::Success) { @@ -884,9 +890,11 @@ LSQUnit::completeStore(int store_idx) // Tell the checker we've completed this instruction. Some stores // may get reported twice to the checker, but the checker can // handle that case. +#if USE_CHECKER if (cpu->checker) { cpu->checker->verify(storeQueue[store_idx].inst); } +#endif } template diff --git a/src/cpu/o3/regfile.hh b/src/cpu/o3/regfile.hh index ade5e4e56..6972f055f 100644 --- a/src/cpu/o3/regfile.hh +++ b/src/cpu/o3/regfile.hh @@ -72,7 +72,7 @@ class PhysRegFile // Will make these registers public for now, but they probably should // be private eventually with some accessor functions. public: - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; /** * Constructs a physical register file with the specified amount of @@ -278,11 +278,11 @@ class PhysRegFile private: /** CPU pointer. */ - FullCPU *cpu; + O3CPU *cpu; public: /** Sets the CPU pointer. */ - void setCPU(FullCPU *cpu_ptr) { cpu = cpu_ptr; } + void setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; } /** Number of physical integer registers. */ unsigned numPhysicalIntRegs; diff --git a/src/cpu/o3/rename.hh b/src/cpu/o3/rename.hh index 42fdf6bf5..581fc8f81 100644 --- a/src/cpu/o3/rename.hh +++ b/src/cpu/o3/rename.hh @@ -55,7 +55,7 @@ class DefaultRename // Typedefs from the Impl. typedef typename Impl::CPUPol CPUPol; typedef typename Impl::DynInstPtr DynInstPtr; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::Params Params; // Typedefs from the CPUPol @@ -115,7 +115,7 @@ class DefaultRename void regStats(); /** Sets CPU pointer. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets the main backwards communication time buffer pointer. */ void setTimeBuffer(TimeBuffer *tb_ptr); @@ -291,7 +291,7 @@ class DefaultRename std::list historyBuffer[Impl::MaxThreads]; /** Pointer to CPU. */ - FullCPU *cpu; + O3CPU *cpu; /** Pointer to main time buffer used for backwards communication. */ TimeBuffer *timeBuffer; diff --git a/src/cpu/o3/rename_impl.hh b/src/cpu/o3/rename_impl.hh index 307022cb8..df8b7f9da 100644 --- a/src/cpu/o3/rename_impl.hh +++ b/src/cpu/o3/rename_impl.hh @@ -162,7 +162,7 @@ DefaultRename::regStats() template void -DefaultRename::setCPU(FullCPU *cpu_ptr) +DefaultRename::setCPU(O3CPU *cpu_ptr) { DPRINTF(Rename, "Setting CPU pointer.\n"); cpu = cpu_ptr; @@ -755,7 +755,7 @@ DefaultRename::updateStatus() DPRINTF(Activity, "Activating stage.\n"); - cpu->activateStage(FullCPU::RenameIdx); + cpu->activateStage(O3CPU::RenameIdx); } } else { // If it's not unblocking, then rename will not have any internal @@ -764,7 +764,7 @@ DefaultRename::updateStatus() _status = Inactive; DPRINTF(Activity, "Deactivating stage.\n"); - cpu->deactivateStage(FullCPU::RenameIdx); + cpu->deactivateStage(O3CPU::RenameIdx); } } } diff --git a/src/cpu/o3/rob.hh b/src/cpu/o3/rob.hh index 6d1402531..b98d7c4c2 100644 --- a/src/cpu/o3/rob.hh +++ b/src/cpu/o3/rob.hh @@ -45,7 +45,7 @@ class ROB typedef TheISA::RegIndex RegIndex; public: //Typedefs from the Impl. - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; typedef typename Impl::DynInstPtr DynInstPtr; typedef std::pair UnmapInfo; @@ -90,7 +90,7 @@ class ROB * is created within. * @param cpu_ptr Pointer to the implementation specific full CPU object. */ - void setCPU(FullCPU *cpu_ptr); + void setCPU(O3CPU *cpu_ptr); /** Sets pointer to the list of active threads. * @param at_ptr Pointer to the list of active threads. @@ -257,7 +257,7 @@ class ROB private: /** Pointer to the CPU. */ - FullCPU *cpu; + O3CPU *cpu; /** Active Threads in CPU */ std::list* activeThreads; diff --git a/src/cpu/o3/rob_impl.hh b/src/cpu/o3/rob_impl.hh index 5a941834b..6277dd68b 100644 --- a/src/cpu/o3/rob_impl.hh +++ b/src/cpu/o3/rob_impl.hh @@ -100,7 +100,7 @@ ROB::name() const template void -ROB::setCPU(FullCPU *cpu_ptr) +ROB::setCPU(O3CPU *cpu_ptr) { cpu = cpu_ptr; diff --git a/src/cpu/o3/thread_state.hh b/src/cpu/o3/thread_state.hh index b6535baa1..19cbffb44 100644 --- a/src/cpu/o3/thread_state.hh +++ b/src/cpu/o3/thread_state.hh @@ -58,11 +58,11 @@ class Process; template struct O3ThreadState : public ThreadState { typedef ThreadContext::Status Status; - typedef typename Impl::FullCPU FullCPU; + typedef typename Impl::O3CPU O3CPU; private: /** Pointer to the CPU. */ - FullCPU *cpu; + O3CPU *cpu; public: /** Whether or not the thread is currently in syscall mode, and * thus able to be externally updated without squashing. @@ -75,12 +75,12 @@ struct O3ThreadState : public ThreadState { bool trapPending; #if FULL_SYSTEM - O3ThreadState(FullCPU *_cpu, int _thread_num) + O3ThreadState(O3CPU *_cpu, int _thread_num) : ThreadState(-1, _thread_num), inSyscall(0), trapPending(0) { } #else - O3ThreadState(FullCPU *_cpu, int _thread_num, Process *_process, int _asid, + O3ThreadState(O3CPU *_cpu, int _thread_num, Process *_process, int _asid, MemObject *mem) : ThreadState(-1, _thread_num, mem, _process, _asid), cpu(_cpu), inSyscall(0), trapPending(0) diff --git a/src/python/m5/objects/AlphaFullCPU.py b/src/python/m5/objects/AlphaFullCPU.py deleted file mode 100644 index 2988305d3..000000000 --- a/src/python/m5/objects/AlphaFullCPU.py +++ /dev/null @@ -1,98 +0,0 @@ -from m5 import build_env -from m5.config import * -from BaseCPU import BaseCPU - -class DerivAlphaFullCPU(BaseCPU): - type = 'DerivAlphaFullCPU' - activity = Param.Unsigned("Initial count") - numThreads = Param.Unsigned("number of HW thread contexts") - - checker = Param.BaseCPU(NULL, "checker") - - cachePorts = Param.Unsigned("Cache Ports") - - decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") - renameToFetchDelay = Param.Unsigned("Rename to fetch delay") - iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " - "delay") - commitToFetchDelay = Param.Unsigned("Commit to fetch delay") - fetchWidth = Param.Unsigned("Fetch width") - - renameToDecodeDelay = Param.Unsigned("Rename to decode delay") - iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " - "delay") - commitToDecodeDelay = Param.Unsigned("Commit to decode delay") - fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") - decodeWidth = Param.Unsigned("Decode width") - - iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " - "delay") - commitToRenameDelay = Param.Unsigned("Commit to rename delay") - decodeToRenameDelay = Param.Unsigned("Decode to rename delay") - renameWidth = Param.Unsigned("Rename width") - - commitToIEWDelay = Param.Unsigned("Commit to " - "Issue/Execute/Writeback delay") - renameToIEWDelay = Param.Unsigned("Rename to " - "Issue/Execute/Writeback delay") - issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " - "to the IEW stage)") - issueWidth = Param.Unsigned("Issue width") - executeWidth = Param.Unsigned("Execute width") - executeIntWidth = Param.Unsigned("Integer execute width") - executeFloatWidth = Param.Unsigned("Floating point execute width") - executeBranchWidth = Param.Unsigned("Branch execute width") - executeMemoryWidth = Param.Unsigned("Memory execute width") - fuPool = Param.FUPool(NULL, "Functional Unit pool") - - iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " - "delay") - renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") - commitWidth = Param.Unsigned("Commit width") - squashWidth = Param.Unsigned("Squash width") - trapLatency = Param.Tick("Trap latency") - fetchTrapLatency = Param.Tick("Fetch trap latency") - - predType = Param.String("Branch predictor type ('local', 'tournament')") - localPredictorSize = Param.Unsigned("Size of local predictor") - localCtrBits = Param.Unsigned("Bits per counter") - localHistoryTableSize = Param.Unsigned("Size of local history table") - localHistoryBits = Param.Unsigned("Bits for the local history") - globalPredictorSize = Param.Unsigned("Size of global predictor") - globalCtrBits = Param.Unsigned("Bits per counter") - globalHistoryBits = Param.Unsigned("Bits of history") - choicePredictorSize = Param.Unsigned("Size of choice predictor") - choiceCtrBits = Param.Unsigned("Bits of choice counters") - - BTBEntries = Param.Unsigned("Number of BTB entries") - BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") - - RASSize = Param.Unsigned("RAS size") - - LQEntries = Param.Unsigned("Number of load queue entries") - SQEntries = Param.Unsigned("Number of store queue entries") - LFSTSize = Param.Unsigned("Last fetched store table size") - SSITSize = Param.Unsigned("Store set ID table size") - - numRobs = Param.Unsigned("Number of Reorder Buffers"); - - numPhysIntRegs = Param.Unsigned("Number of physical integer registers") - numPhysFloatRegs = Param.Unsigned("Number of physical floating point " - "registers") - numIQEntries = Param.Unsigned("Number of instruction queue entries") - numROBEntries = Param.Unsigned("Number of reorder buffer entries") - - instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") - - function_trace = Param.Bool(False, "Enable function trace") - function_trace_start = Param.Tick(0, "Cycle to start function trace") - - smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") - smtFetchPolicy = Param.String("SMT Fetch policy") - smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") - smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") - smtIQPolicy = Param.String("SMT IQ Sharing Policy") - smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") - smtROBPolicy = Param.String("SMT ROB Sharing Policy") - smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") - smtCommitPolicy = Param.String("SMT Commit Policy") diff --git a/src/python/m5/objects/AlphaO3CPU.py b/src/python/m5/objects/AlphaO3CPU.py new file mode 100644 index 000000000..f14f8c88e --- /dev/null +++ b/src/python/m5/objects/AlphaO3CPU.py @@ -0,0 +1,98 @@ +from m5 import build_env +from m5.config import * +from BaseCPU import BaseCPU + +class DerivAlphaO3CPU(BaseCPU): + type = 'DerivAlphaO3CPU' + activity = Param.Unsigned("Initial count") + numThreads = Param.Unsigned("number of HW thread contexts") + + checker = Param.BaseCPU(NULL, "checker") + + cachePorts = Param.Unsigned("Cache Ports") + + decodeToFetchDelay = Param.Unsigned("Decode to fetch delay") + renameToFetchDelay = Param.Unsigned("Rename to fetch delay") + iewToFetchDelay = Param.Unsigned("Issue/Execute/Writeback to fetch " + "delay") + commitToFetchDelay = Param.Unsigned("Commit to fetch delay") + fetchWidth = Param.Unsigned("Fetch width") + + renameToDecodeDelay = Param.Unsigned("Rename to decode delay") + iewToDecodeDelay = Param.Unsigned("Issue/Execute/Writeback to decode " + "delay") + commitToDecodeDelay = Param.Unsigned("Commit to decode delay") + fetchToDecodeDelay = Param.Unsigned("Fetch to decode delay") + decodeWidth = Param.Unsigned("Decode width") + + iewToRenameDelay = Param.Unsigned("Issue/Execute/Writeback to rename " + "delay") + commitToRenameDelay = Param.Unsigned("Commit to rename delay") + decodeToRenameDelay = Param.Unsigned("Decode to rename delay") + renameWidth = Param.Unsigned("Rename width") + + commitToIEWDelay = Param.Unsigned("Commit to " + "Issue/Execute/Writeback delay") + renameToIEWDelay = Param.Unsigned("Rename to " + "Issue/Execute/Writeback delay") + issueToExecuteDelay = Param.Unsigned("Issue to execute delay (internal " + "to the IEW stage)") + issueWidth = Param.Unsigned("Issue width") + executeWidth = Param.Unsigned("Execute width") + executeIntWidth = Param.Unsigned("Integer execute width") + executeFloatWidth = Param.Unsigned("Floating point execute width") + executeBranchWidth = Param.Unsigned("Branch execute width") + executeMemoryWidth = Param.Unsigned("Memory execute width") + fuPool = Param.FUPool(NULL, "Functional Unit pool") + + iewToCommitDelay = Param.Unsigned("Issue/Execute/Writeback to commit " + "delay") + renameToROBDelay = Param.Unsigned("Rename to reorder buffer delay") + commitWidth = Param.Unsigned("Commit width") + squashWidth = Param.Unsigned("Squash width") + trapLatency = Param.Tick("Trap latency") + fetchTrapLatency = Param.Tick("Fetch trap latency") + + predType = Param.String("Branch predictor type ('local', 'tournament')") + localPredictorSize = Param.Unsigned("Size of local predictor") + localCtrBits = Param.Unsigned("Bits per counter") + localHistoryTableSize = Param.Unsigned("Size of local history table") + localHistoryBits = Param.Unsigned("Bits for the local history") + globalPredictorSize = Param.Unsigned("Size of global predictor") + globalCtrBits = Param.Unsigned("Bits per counter") + globalHistoryBits = Param.Unsigned("Bits of history") + choicePredictorSize = Param.Unsigned("Size of choice predictor") + choiceCtrBits = Param.Unsigned("Bits of choice counters") + + BTBEntries = Param.Unsigned("Number of BTB entries") + BTBTagSize = Param.Unsigned("Size of the BTB tags, in bits") + + RASSize = Param.Unsigned("RAS size") + + LQEntries = Param.Unsigned("Number of load queue entries") + SQEntries = Param.Unsigned("Number of store queue entries") + LFSTSize = Param.Unsigned("Last fetched store table size") + SSITSize = Param.Unsigned("Store set ID table size") + + numRobs = Param.Unsigned("Number of Reorder Buffers"); + + numPhysIntRegs = Param.Unsigned("Number of physical integer registers") + numPhysFloatRegs = Param.Unsigned("Number of physical floating point " + "registers") + numIQEntries = Param.Unsigned("Number of instruction queue entries") + numROBEntries = Param.Unsigned("Number of reorder buffer entries") + + instShiftAmt = Param.Unsigned("Number of bits to shift instructions by") + + function_trace = Param.Bool(False, "Enable function trace") + function_trace_start = Param.Tick(0, "Cycle to start function trace") + + smtNumFetchingThreads = Param.Unsigned("SMT Number of Fetching Threads") + smtFetchPolicy = Param.String("SMT Fetch policy") + smtLSQPolicy = Param.String("SMT LSQ Sharing Policy") + smtLSQThreshold = Param.String("SMT LSQ Threshold Sharing Parameter") + smtIQPolicy = Param.String("SMT IQ Sharing Policy") + smtIQThreshold = Param.String("SMT IQ Threshold Sharing Parameter") + smtROBPolicy = Param.String("SMT ROB Sharing Policy") + smtROBThreshold = Param.String("SMT ROB Threshold Sharing Parameter") + smtCommitPolicy = Param.String("SMT Commit Policy")