From: Clifford Wolf <clifford@clifford.at>
Date: Tue, 11 Mar 2014 10:59:58 +0000 (+0100)
Subject: Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
X-Git-Tag: yosys-0.3.0~68
X-Git-Url: https://git.libre-soc.org/?a=commitdiff_plain;h=bada3ee815c05933723a64234106ab68b7599568;p=yosys.git

Fixed yosys path in tests/techmap/mem_simple_4x1_runtest.sh
---

diff --git a/tests/techmap/mem_simple_4x1_runtest.sh b/tests/techmap/mem_simple_4x1_runtest.sh
index 541da483e..e2c6303da 100644
--- a/tests/techmap/mem_simple_4x1_runtest.sh
+++ b/tests/techmap/mem_simple_4x1_runtest.sh
@@ -2,7 +2,7 @@
 
 set -ev
 
-yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
+../../yosys -b 'verilog -noattr' -o mem_simple_4x1_synth.v -p 'proc; opt; memory -nomap; techmap -map mem_simple_4x1_map.v;; techmap; opt; abc;; stat' mem_simple_4x1_uut.v
 
 iverilog -o mem_simple_4x1_gold_tb mem_simple_4x1_tb.v mem_simple_4x1_uut.v
 iverilog -o mem_simple_4x1_gate_tb mem_simple_4x1_tb.v mem_simple_4x1_synth.v mem_simple_4x1_cells.v